Getting Started with Embedded Coder Support Package for Intel® SoC Devices
This example shows you how to use Embedded Coder Support Package for Altera® SoC Platform to run a Simulink® model on an Intel SoC FPGA hardware.
Embedded Coder Support Package for Intel SoC Devices enables you to create and run Simulink models on an Intel SoC FPGA hardware. You can verify the generated code on Intel SoC FPGA hardware without actual hardware. You can also collect execution time measurements for an algorithm implemented in Simulink to aid refining and optimizing your algorithm.
- Intel® SoC FPGA Embedded Design Suite (version 16.1)
This example requires one of the following boards:
- Altera Cyclone V SoC development board
- Arrow SoCKit development board
Configure model for code generation
In this task, you create and configure simple model. Then you build and run an executable on Intel SoC FPGA hardware.
1. In MATLAB, select HOME > New > Simulink Model.
2. To configure the model for Altera Cyclone V SoC development board target follow the steps shown in the figure below:
3. Open Simulink browser. Click on Simulink > Commonly Used Blocks tab. Drag and drop a Constant block, a Gain block and an Out1 block into your model. Connect these three blocks as shown in the figure below and generate and run code on Intel SoC FPGA hardware by first saving the model and then clicking on Build model button:
The MathWorks software compiles and links the generated code on the host computer. Then, the software loads and runs the binary executable on the Intel SoC FPGA hardware.
A command window pops-up showing that the executable has started running on the Intel SoC FPGA hardware.
4. Close the command window. Use the following MATLAB commands to terminate the executable running on the hardware:
hsoc = alterasoc(); stop(hsoc, 'alterasoc_gettingstarted');
5. To interact with the code running on the Intel SoC FPGA hardware see Code Verification and Validation with PIL and External Mode example.
This example introduced the workflow for configuring, generating code from a Simulink model and running the executable on the Intel SoC FPGA hardware.