Deep Learning Processor IP Core
The generated deep learning (DL) processor IP core is a standard AXI interface IP core that contains:
AXI slave interface to program the DL processor IP core.
AXI master interfaces to access the external memory of the target board.
To generate the DL processor IP core, use the HDL Coder™ IP core generation workflow. The generated IP core contains a standard set of registers and the generated IP core report. For more information, see Deep Learning Processor Register Map.
The DL processor IP core reads inputs from the external memory and sends outputs to the external memory. The external memory buffer allocation is calculated by the compiler based on the network size and your hardware design. For more information, see Use the Compiler Output for System Integration.
The input and output data stored in the external memory in a predefined format. For more information, see External Memory Data Format.