MATLAB Controlled Deep Learning Processor

To rapidly prototype the deep learning networks on FPGAs from MATLAB^®, use a MATLAB controlled deep learning processor. The processor integrates the generic deep learning processor with the HDL Verifier™ MATLAB as AXI Master IP. For more information on:

• Generic deep learning processor IP, see Generate Custom Generic Deep Learning Processor IP Core.

• MATLAB as AXI Master IP, see Set Up AXI Manager (HDL Verifier).

You can use this processor to run neural networks with various inputs, weights, and biases on the same FPGA platform because the deep learning processor IP core can handle tensors and shapes of any sizes. Before you use the MATLAB as AXI Master, make sure that you have installed the HDL Verifier support packages for the FPGA boards. This figure shows the MATLAB controlled deep learning processor architecture.

To integrate the generic deep learning processor IP with the MATLAB as AXI Master, use the AXI4 Slave interface of the deep learning processor IP core. By using a JTAG or PCI express interface, the IP responds to read or write commands from MATLAB. Therefore, you can use the MATLAB controlled deep learning processor to deploy the deep learning neural network to the FPGA boards from MATLAB, perform operations specified by the network architecture, and then return the predicted results to MATLAB. For example, see Image Classification Using Neural Network on FPGA.