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Discrete FIR Filter

Finite impulse response filter

  • Library:
  • DSP HDL Toolbox / Filtering

  • Discrete FIR Filter block

Description

The Discrete FIR Filter block models finite-impulse response filter architectures optimized for HDL code generation. The block accepts scalar or frame-based input, and provides an option for programmable coefficients. It provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the block models architectural latency including pipeline registers and resource sharing.

The block provides three filter structures. The direct form systolic architecture provides a fully parallel implementation that makes efficient use of Intel® and Xilinx® DSP blocks. The direct form transposed architecture is a fully parallel implementation and is suitable for FPGA and ASIC applications. The partly serial systolic architecture provides a configurable serial implementation that makes efficient use of FPGA DSP blocks. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.

All three filter structures remove multipliers for zero-valued coefficients, such as in half-band filters and Hilbert transforms. When you use scalar input data, all filter structures share multipliers for symmetric and antisymmetric coefficients. Frame-based filters do not implement symmetry optimization.

The latency between valid input data and the corresponding valid output data depends on the filter structure, serialization options, the number of coefficients, and whether the coefficient values provide optimization opportunities. For details of structure and latency, see the Algorithm section.

For a FIR filter with multichannel support, use the Discrete FIR Filter (Simulink) block instead.

Ports

Input

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Input data, specified as a scalar or column vector of real or complex values. The vector size must be a power of 2 in the range from 1 to 64. When the input data type is an integer type or a fixed-point type, the block uses fixed-point arithmetic for internal calculations.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: fixed point | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

Control signal that indicates if the input data is valid. When valid is 1 (true), the block captures the values from the input data port. When valid is 0 (false), the block ignores the values from the input data port.

Data Types: Boolean

Filter coefficients, specified as a row vector of real or complex values. You can change the input coefficients at any time. When you use scalar input data, the size of the coefficient vector depends on the size and symmetry of the sample coefficients specified in the Coefficients prototype parameter. The prototype specifies a sample coefficient vector that is representative of the symmetry and zero-valued locations of the expected input coefficients. The block uses the prototype to optimize the filter by sharing multipliers for symmetric or antisymmetric coefficients, and removing multipliers for zero-valued coefficients. Therefore, provide only the nonduplicate coefficients at the port. For example, if you set the Coefficients prototype parameter to a symmetric 14-tap filter, the block expects a vector of 7 values on the coeff input port. You must still provide zeros in the input coeff vector for the nonduplicate zero-valued coefficients.

When you use frame-based input data, the block does not optimize the filter for coefficient symmetry. The block still uses the Coefficients prototype to remove multipliers for zero-valued coefficients. At the coeff input port, specify a vector that is the same size as the prototype.

double and single data types are supported for simulation, but not for HDL code generation.

Dependencies

To enable this port, set Coefficients source to Input port (Parallel interface).

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | fixed point

Control signal that clears internal states. When reset is 1 (true), the block stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this port, on the Control Ports tab, select Enable reset input port.

Data Types: Boolean

Output

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Filtered output data, returned as a scalar or column vector of real or complex values. The dimensions of the output match the dimensions of the input. When the input data type is a floating-point type, the output data inherits the data type of the input data. When the input data type is an integer type or a fixed-point type, the Output parameter on the Data Types tab controls the output data type.

Data Types: fixed point | single | double
Complex Number Support: Yes

Control signal that indicates if the data from the output data port is valid. When valid is 1 (true), the block returns valid data from the output data port. When valid is 0 (false), the values from the output data port are not valid.

Data Types: Boolean

Control signal that indicates that the block is ready for new input data sample on the next cycle. When ready is 1 (true), you can specify the data and valid inputs for the next time step. When ready is 0 (false), the block ignores any input data in the next time step.

When using the partly serial architecture, the block processes one sample at a time. If your design waits for this block to return ready set to 0 before setting the input valid to 0 (false), then one additional cycle of input data arrives at the port. The block stores this additional data while processing the current data, and then does not set ready to 1 (true), until your model processes the additional input data.

Dependencies

To enable this port, set Filter structure to Partly serial systolic.

Data Types: Boolean

Parameters

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Main

You can enter constant filter coefficients as a parameter or provide time-varying filter coefficients using an input port.

Selecting Input port (Parallel interface) enables the coeff port on the block and the Coefficients prototype parameter. Specify a prototype to enable the block to optimize the filter implementation according to the values of your coefficients. To use Input port (Parallel interface), set the Filter structure parameter to Direct form systolic or Direct form transposed.

When you use programmable coefficients with frame-based input, the filter does not optimize the filter for coefficient symmetry. Also, the output after a change of coefficient values may not exactly match the output in the scalar case. This difference is because the subfilter calculations are done at different times relative to the input coefficient values, compared with the scalar implementation.

Discrete FIR filter coefficients, specified as a vector of real or complex values. You can also specify the vector as a workspace variable or as a call to a filter design function. When the input data type is a floating-point type, the block casts the coefficients to the same data type as the input. When the input data type is an integer type or a fixed-point type, you can set the data type of the coefficients on the Data Types tab.

Example: firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0])

Dependencies

To enable this parameter, set Coefficients source to Property.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

Prototype filter coefficients, specified as a vector of real or complex values. The prototype specifies a sample coefficient vector that is representative of the symmetry and zero-valued locations of the expected input coefficients. If all of your input coefficient vectors have the same symmetry and zero-valued coefficient locations, set Coefficients prototype to one of those vectors. If your coefficients are unknown or not expected to share symmetry or zero-valued locations, set Coefficients prototype to []. The block uses the prototype to optimize the filter by sharing multipliers for symmetric or antisymmetric coefficients, and removing multipliers for zero-valued coefficients.

When you use frame-based input data, the block does not optimize the filter for coefficient symmetry. The block still uses the Coefficients prototype to remove multipliers for zero-valued coefficients. At the coeff input port, specify a vector that is the same size as the prototype.

When you use scalar input data, coefficient optimizations affect the expected size of the vector on the coeff port. Provide only the nonduplicate coefficients at the port. For example, if you set the Coefficients prototype parameter to a symmetric 14-tap filter, the block shares one multiplier between each pair of duplicate coefficients, so the block expects a vector of 7 values on the coeff port. You must still provide zeros in the input coeff vector for the nonduplicate zero-valued coefficients.

Dependencies

To enable this parameter, set Coefficients source to Input port (Parallel interface).

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

Specify the HDL filter architecture as one of these structures:

  • Direct form systolic — This architecture provides a fully parallel filter implementation that makes efficient use of Intel and Xilinx DSP blocks. For architecture details, see Fully Parallel Systolic Architecture.

  • Direct form transposed — This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For architecture details, see Fully Parallel Transposed Architecture.

  • Partly serial systolic — This architecture provides a serial filter implementation and options for tradeoffs between throughput and resource utilization. It makes efficient use of Intel and Xilinx DSP blocks. The block implements a serial L-coefficient filter with M multipliers and requires input samples that are at least N cycles apart, such that L = N×M. You can specify either M or N. For this implementation, the block provides an output port, ready, that indicates when the block is ready for new input data. For architecture details, see Partly Serial Systolic Architecture (1 < N < L) and Fully Serial Systolic Architecture (N ≥ L). You cannot use frame-based input with the partly serial architecture.

All implementations remove multipliers for zero-valued coefficients. When you use scalar input data, all implementations share multipliers for symmetric and antisymmetric coefficients. Frame-based filters do not implement symmetry optimization.

You can specify the rule that the block uses to serialize the filter as either:

  • Minimum number of cycles between valid input samples – Specify a requirement for input data timing using the Number of cycles parameter.

  • Maximum number of multipliers – Specify a requirement for resource usage using the Number of multipliers parameter.

For a filter with L coefficients, the block implements a serial filter with not more than M multipliers and requires input samples that are at least N cycles apart, such that L = N×M. The block might remove multipliers when it applies coefficient optimizations, so the actual M or N value of the filter implementation can be lower than the value that you specified.

Dependencies

To enable this parameter, set the Filter structure parameter to Partly serial systolic.

Serialization requirement for input timing, specified as a positive integer. This parameter represents N, the minimum number of cycles between valid input samples. In this case, the block calculates M = L/N. To implement a fully-serial architecture, set Number of cycles greater than the filter length, L, or to Inf.

The block might remove multipliers when it applies coefficient optimizations, so the actual M and N values of the filter can be lower than the value you specified.

Dependencies

To enable this parameter, set Filter structure to Partly serial systolic and set Specify serialization factor as to Minimum number of cycles between valid input samples.

Serialization requirement for resource usage, specified as a positive integer. This parameter represents M, the maximum number of multipliers in the filter implementation. In this case, the block calculates N = L/M. If the input data is complex, the block allocates floor(M/2) multipliers for the real part of the filter and floor(M/2) multipliers for the imaginary part of the filter. To implement a fully-serial architecture, set Number of multipliers to 1 for real input with real coefficients, 2 for complex input and real coefficients or real coefficients with complex input, or 3 for complex input and complex coefficients.

The block might remove multipliers when it applies coefficient optimizations, so the actual M and N values of the filter can be lower than the value you specified.

Dependencies

To enable this parameter, set the Filter structure to Partly serial systolic, and set Specify serialization factor as to Maximum number of multipliers.

Data Types

Rounding mode for type-casting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores this parameter. For more details, see Rounding Modes.

Overflow handling for type-casting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores this parameter. For more details, see Overflow Handling.

The block casts the filter coefficients to this data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is floating point, the block ignores this parameter.

The recommended data type for this parameter is Inherit: Same word length as input.

The block returns a warning or error if:

  • The coefficients data type does not have enough fractional length to represent the coefficients accurately.

  • The coefficients data type is unsigned while the coefficients include negative values.

Dependencies

To enable this parameter, set Coefficients source to Property.

The block casts the output of the filter to this data type. The quantization uses the settings of the Rounding mode and Overflow mode parameters. When the input data type is floating point, the block ignores this parameter.

The block increases the word length for full precision inside each filter tap and casts the final output to the specified type. The maximum final internal data type (WF) depends on the input data type (WI), the coefficient data type (WC), and the number of coefficients (L) and is given by

WF = WI + WC + ceil(log2(L)).

When you specify a fixed set of coefficients, because the coefficient values limit the potential growth, usually the actual full-precision internal word length is smaller than WF.

When you use programmable coefficients, the block cannot calculate the dynamic range, and the internal data type is always WF.

Control Ports

Select this parameter to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Select this parameter to connect the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink®. When you clear this parameter, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Algorithms

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The filter architectures for the Discrete FIR Filter block are shared with other blocks and described in detail on the FIR Filter Architectures for FPGAs and ASICs page. The sections here show the hardware resources and synthesized clock speed for the Discrete FIR Filter block configured with each filter architecture.

Extended Capabilities

Version History

Introduced in R2017a

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