Euler to NED Transformation HDL Optimized

Computes Euler to North-East-Down transformation using pipelined or burst architecture and generates optimized HDL code

Since R2022b

• 

Libraries:
Fixed-Point Designer HDL Support / Coordinate Transformations

Description

The Euler to NED Transformation HDL Optimized block provides two architectures that implement Euler to North-East-Down (NED) transformation using a CORDIC rotation kernel for FPGA and ASIC applications.

You can select an architecture that optimizes for either throughput or area.

• Pipelined — Use this architecture for high-throughput applications.

• Burst — Use this architecture for a minimum resource implementation.

The Euler to NED Transformation HDL Optimized block provides hardware-friendly control signals.

Ports

Input

U In — Input array

3-by-1 vector

Input array, specified as a 3-by-1 vector.

Fixed-point inputs must use binary-point scaling.

Example: UIn = [0;0;1]

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point
Complex Number Support: Yes

Angle In — Angles to rotate by

3-by-1 vector

Angles to rotate by, specified as a 3-by-1 real-valued vector containing the angles phi, theta, and psi in radians.

Example: AngleIn = [phi;theta;psi]

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Valid In — Whether input is valid

Boolean scalar

Whether input is valid, specified as a Boolean scalar. This control signal indicates when the data from the U In and Angle In input ports are valid. When this value is 1 (true), the block captures the values at the input ports U In and Angle In. When this value is 0 (false), the block ignores the input samples.

Data Types: Boolean

Restart — Whether to clear internal states

Boolean scalar

Whether to clear internal states, specified as a Boolean scalar. When this value is 1 (true), the block stops the current calculation and clears all internal states. When this value is 0 (false) and the Valid In value is 1 (true), the block begins a new subframe.

Data Types: Boolean

Output

U Out — Rotated array

3-by-1 vector

Rotated array, returned as a 3-by-1 vector.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Valid Out — Whether output data is valid

boolean scalar

Whether the output data is valid, returned as a Boolean scalar. When the value of this control signal is 1 (true), the block has successfully computed the output U Out. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

Ready — Whether block is ready for input

Boolean scalar

Whether the block is ready for input, returned as a Boolean scalar. This control signal indicates when the block is ready for new input data. When this value is 1 (true) and Valid In value is 1 (true), the block accepts input data in the next time step. When this value is 0 (false), the block ignores input data in the next time step.

Data Types: Boolean

Parameters

Architecture — Architecture type

Pipelined (default) | Burst

This parameter specifies the type of architecture.

• Pipelined — Select this value to specify low-latency architecture.

• Burst — Select this value to specify minimum resource architecture.

Programmatic Use

Block Parameter: Architecture

Type: character vector

Values: 'Pipelined' | 'Burst'

Default: 'Pipelined'

Algorithms

Euler-NED Transformation

The Euler to North-East-Down (NED) transformation is carried out by the successive application of these three rotation matrices.

$$\begin{array}{l}{R}_{\varphi }=\left[\begin{array}{ccc}1& 0& 0\\ 0& \cos (\varphi )& -\sin (\varphi )\\ 0& \sin (\varphi )& \cos (\varphi )\end{array}\right]\\ R_{\theta }=\left[\begin{array}{ccc}\cos (\theta )& 0& \sin (\theta )\\ 0& 1& 0\\ -\sin (\theta )& 0& \cos (\theta )\end{array}\right]\\ R_{\psi }=\left[\begin{array}{ccc}\cos (\psi )& -\sin (\psi )& 0\\ \sin (\psi )& \cos (\psi )& 0\\ 0& 0& 1\end{array}\right]\end{array}$$

Multiplying these matrices together gives the total transformation.

$$\begin{array}{c}A=R_{\psi }{R}_{\theta }{R}_{\varphi }\\ =\left[\begin{array}{ccc}\cos (\psi )\cos (\theta )& \cos (\psi )\sin (\varphi )\sin (\theta )-\cos (\varphi )\sin (\psi )& \sin (\varphi )\sin (\psi )+\cos (\varphi )\cos (\psi )\sin (\theta )\\ \cos (\theta )\sin (\psi )& \cos (\varphi )\cos (\psi )+\sin (\varphi )\sin (\psi )\sin (\theta )& \cos (\varphi )\sin (\psi )\sin (\theta )-\cos (\psi )\sin (\varphi )\\ -\sin (\theta )& \cos (\theta )\sin (\varphi )& \cos (\varphi )\cos (\theta )\end{array}\right]\end{array}$$

You can transform between two frames related by the angles ϕ, θ

, and ψ by multiplying a vector in an initial frame by the matrix above.

CORDIC Algorithm

CORDIC is an acronym for COordinate Rotation Digital Computer. The Givens rotation-based CORDIC algorithm is one of the most hardware-efficient algorithms available because it requires only iterative shift-add operations. It is an iterative algorithm that approximates the solution by converging toward the ideal point. Using CORDIC, you can calculate various functions such as sine and cosine.

To use CORDIC to solve the Euler-NED transformation, CORDIC Givens rotations are applied sequentially in the appropriate subspaces of the initial space. First, rotate by ϕ in the yz-plane, then rotate by -θ in the xz-plane, then rotate by ψ in the xy-plane.

Performance

This resource and performance data is the synthesis result from the generated HDL targeted to a Virtex^®-7.

Resource Usage

Algorithm	Flip Flops	LUT	LUTRAM	DSPs
Pipelined CORDIC (sfix14En10)	3141	86	3973	0
Resource Shared CORDIC (sfix14En10)	337	659	0	0

Static Timing Analysis

Algorithm	Clock Frequency (MHz)	Latency (Cycles)	Latency (ns)
Pipelined CORDIC (sfix14En10)	347	63	181
Resource Shared CORDIC (sfix14En10)	347	57	164

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Supports fixed-point data types only. Fixed-point data types must use binary-point scaling.

Generated C/C++ code will have timing of the HDL block.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

Supports fixed-point data types only. Fixed-point data types must use binary-point scaling.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2022b