Bit Rotate

R2026b

Rotate input signal by bit positions

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Bit Rotate block

To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.

Libraries:
HDL Coder / Logic and Bit Operations

Description

The Bit Rotate block rotates the input signal left or right by the specified number of bit positions.

Ports

Input

Port_1 — Input Signal

scalar | vector

Input signal on which the bit-rotation is performed.

• Minimum bit width: 2

• Maximum bit width: 128

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Output

Port_1 — Output Signal

scalar | vector

Output signal that is bit-rotated. The output signal has the same data type as the input signal.

Parameters

Rotate Mode — Specifies direction of rotation, left or right

Rotate Left (default) | Rotate Right

Specifies direction of rotation, left or right.

Programmatic Use

Block parameter: mode

Type: string scalar | character vector

Value: "Rotate Left" | "Rotate Right"

Default: 'Rotate Left'

Rotate Length — Specifies the number of bits to rotate

0 (default) | integer greater than or equal to zero

Specifies the number of bits to rotate.

Programmatic Use

Block parameter: N

Type: string scalar | character vector

Value: integer greater than or equal to zero

Default: '0'

Programmatic Use: Add Block

To add the block programmatically, use the add_block function with one of these library block paths as the source.

"hdlsllib/Logic and Bit Operations/Bit Rotate"

Example: add_block("hdlsllib/Logic and Bit Operations/Bit Rotate","myModel/myBlock",MakeNameUnique="on")

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline.
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes.

Version History

Introduced in R2014a

R2026a: Specify synthesis attributes for blocks and block output signals

Use the SynthesisAttributes HDL block property to specify the synthesis attributes for the block and its output signals. HDL Coder includes these attributes in the generated HDL code.