createFloatingPointTargetConfig

Class: hdlcoder.FloatingPointTargetConfig
Package: hdlcoder

Create floating-point target configuration for floating-point library that you specify

Syntax

fpconfig = hdlcoder.createFloatingPointTargetConfig(library)
fpconfig = hdlcoder.createFloatingPointTargetConfig(library,Name,Value)


Description

To create a floating-point target configuration object for a floating-point library, use the hdlcoder.createFloatingPointTargetConfig function. You can create a floating-point configuration object for these libraries:

• Native Floating Point

• Altera^® Megafunctions (ALTERA FP Functions)

• Altera Megafunctions (ALTFP)

• Xilinx^® LogiCORE^®

fpconfig = hdlcoder.createFloatingPointTargetConfig(library) creates an hdlcoder.FloatingPointTargetConfig object for a given floating-point library.

fpconfig = hdlcoder.createFloatingPointTargetConfig(library,Name,Value) creates an hdlcoder.FloatingPointTargetConfig object with additional options specified by one or more Name,Value pair arguments. Name can also be a property name and Value is the corresponding value. Name must appear inside single quotes (''). You can specify several name-value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Input Arguments

Library — Floating point library name

None (default) | NATIVEFLOATINGPOINT | ALTERAFPFUNCTIONS | ALTFP | XILINXLOGICORE

Floating-point library name, specified as a character vector

Example: 'ALTERAFPFUNCTIONS'

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

The name-value pair arguments that you can specify depend on the library that you select for creating the floating-point configuration.

Native Floating Point

HandleDenormals — Specify whether to handle denormal numbers in your design

'Auto' (default) | 'on' | 'off'

Specify whether you want HDL Coder™ to handle denormal numbers in your design. Specify this property as a character vector. Denormal numbers are nonzero numbers that are smaller than the smallest normal number. To specify this property, for Library, select NATIVEFLOATINGPOINT.

LatencyStrategy — Specify whether to use maximum or minimum latency for the native floating-point operator

'MAX' (default) | 'MIN' | 'ZERO'

Specify whether you want HDL Coder to use maximum or minimum latency setting for the floating-operators that your design uses. Specify this property as a character vector. To specify this property, for Library, select NATIVEFLOATINGPOINT

MantissaMultiplyStrategy — Specify how you want HDL Coder to implement the mantissa multiplication operation when your design uses floating-point multipliers

'FullMultiplier' (default) | 'PartMultiplierPartAddShift' | 'NoMultiplierFullAddShift'

Specify how you want HDL Coder to implement the mantissa multiplication process for floating-point multipliers in your design. With this option, you can control the DSP usage on the target platform for your design. To learn more, see Mantissa Multiplier Strategy.

Altera FP Functions

InitializeIPPipelinesToZero — Specify whether to initialize pipeline registers in the Altera Megafunction IP to zero

true (default) | false

Specify whether you want HDL Coder to initialize pipeline registers in the Altera Megafunction IP to zero. Specify this property as a logical. To avoid potential numerical mismatches in the HDL simulation, leave InitializeIPPipelinesToZero set to true. To specify this property, for Library, select ALTERAFPFUNCTIONS.

ALTFP and Xilinx LogiCORE

LatencyStrategy — Specify whether to use maximum or minimum latency when mapping your design to FPGA floating-point target libraries

'MIN' (default) | 'MAX'

Specify whether you want the design to map to minimum or maximum latency with Xilinx LogiCORE or Altera Megafunction IP. Specify this property as a character vector.

Objective — Specify whether to optimize the design for speed or area when mapping your design to FPGA floating-point target libraries

'SPEED' (default) | 'AREA'

Specify whether you want the design to map to minimum or maximum latency with Xilinx LogiCORE or Altera Megafunction IP. Specify this property as a character vector.

Examples

Create Floating-Point Configuration with Native Floating Point and Generate Code

This example shows how to create a floating-point target configuration with the native floating-point support in HDL Coder, and then generate code.

Create a Floating-Point Target Configuration

To create a floating-point configuration, use hdlcoder.createFloatingPointTargetConfig.

load_system('sfir_single');
fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT')

fpconfig = 

  FloatingPointTargetConfig with properties:

            Library: 'NativeFloatingPoint'
    LibrarySettings: [1×1 fpconfig.NFPLatencyDrivenMode]
           IPConfig: [1×1 hdlcoder.FloatingPointTargetConfig.IPConfig]

Specify Custom Library Settings

Optionally, to customize the floating-point configuration, specify custom library settings.

fpconfig.LibrarySettings.HandleDenormals = 'off';
fpconfig.LibrarySettings.LatencyStrategy = 'MIN';
fpconfig.LibrarySettings.MantissaMultiplyStrategy = 'NoMultiplierFullAddShift';
fpconfig.LibrarySettings

ans = 

  NFPLatencyDrivenMode with properties:

             LatencyStrategy: 'MIN'
             HandleDenormals: 'off'
    MantissaMultiplyStrategy: 'NoMultiplierFullAddShift'
                     Version: '1.0.0'

View Latency of Native Floating Point Operators

The IPConfig object displays the maximum and minimum latency values of the floating-point operators.

fpconfig.IPConfig

ans = 

       Name              DataType            MaxLatency    MinLatency
    __________    _______________________    __________    __________

    'ABS'         'SINGLE'                    0             0        
    'ADDSUB'      'SINGLE'                   12             7        
    'ATAN'        'SINGLE'                   36            36        
    'ATAN2'       'SINGLE'                   42            42        
    'CONVERT'     'NUMERICTYPE_TO_SINGLE'     6             6        
    'CONVERT'     'SINGLE_TO_NUMERICTYPE'     6             6        
    'COS'         'SINGLE'                   27            27        
    'DIV'         'SINGLE'                   32            32        
    'EXP'         'SINGLE'                   23            23        
    'FIX'         'SINGLE'                    3             3        
    'LOG'         'SINGLE'                   20            20        
    'MINMAX'      'SINGLE'                    3             3        
    'MOD'         'SINGLE'                    0             0        
    'MUL'         'SINGLE'                    8             8        
    'POW2'        'SINGLE'                    2             2        
    'RECIP'       'SINGLE'                   19            19        
    'RELOP'       'SINGLE'                    3             3        
    'REM'         'SINGLE'                    0             0        
    'ROUNDING'    'SINGLE'                    5             5        
    'RSQRT'       'SINGLE'                   17            17        
    'SIGNUM'      'SINGLE'                    0             0        
    'SIN'         'SINGLE'                   27            27        
    'SINCOS'      'SINGLE'                   27            27        
    'SQRT'        'SINGLE'                   28            28        
    'UMINUS'      'SINGLE'                    0             0        

Generate Code

makehdl('sfir_single/symmetric_fir','FloatingPointTargetConfiguration',fpconfig, ...
                    'TargetDirectory','C:/NativeFloatingPoint/hdlsrc')

### Generating HDL for 'sfir_single/symmetric_fir'.
### Starting HDL check.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 30 cycles.
### Output port 1: 30 cycles.
### Begin VHDL Code Generation for 'sfir_single'.
### Working on sfir_single/symmetric_fir/nfp_add_comp as C:\NativeFloatingPoint\hdlsrc\sfir_single\nfp_add_comp.vhd.
### Working on sfir_single/symmetric_fir/nfp_mul_comp as C:\NativeFloatingPoint\hdlsrc\sfir_single\nfp_mul_comp.vhd.
### Working on sfir_single/symmetric_fir as C:\NativeFloatingPoint\hdlsrc\sfir_single\symmetric_fir.vhd.
### Generating package file C:\NativeFloatingPoint\hdlsrc\sfir_single\symmetric_fir_pkg.vhd.
### Creating HDL Code Generation Check Report file://C:\NativeFloatingPoint\hdlsrc\sfir_single\symmetric_fir_report.html
### HDL check for 'sfir_single' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated VHDL code is saved in the hdlsrc folder.