Target Workflow Parameters

This page describes the configuration parameters in the Workflow Settings section of the HDL Code Generation > Target pane of the Configuration Parameters dialog box. Use the parameters in this section to specify target workflow options.

Workflow

Specify your target workflow. The setting for this parameter determines the available parameters in the Target pane.

Settings

Default: Generic ASIC/FPGA

The options are:

Generic ASIC/FPGA

Generate and verify HDL code from your Simulink^® model and synthesize the code for a specific ASIC or FPGA device. When you select this option, you can select the target device chip from one of the devices listed in Generic ASIC/FPGA Hardware.

IP Core Generation

Generate RTL code and a custom HDL IP core from your Simulink model. For more information, see Targeting FPGA & SoC Hardware Overview.

When you select IP Core Generation, the HDL Code tab in the Simulink Toolstrip updates to allow you to generate an IP core directly from the toolstrip. For more information, see Comparison of IP Core Generation Techniques.

The IP core is a shareable and modular HDL component that consists of IP core definition files, HDL code generated for your algorithm, a C header file with the register address map, and the IP core report. See:

You can select a hardware platform to generate IP core for from the platforms listed in IP Core Generation Hardware.

FPGA-in-the-Loop

Test your Simulink model on a target FPGA. This setting requires HDL Verifier™ and the HDL Workflow Advisor.

Simulink Real-Time FPGA I/O

Generate HDL code from your Simulink model and deploy the code to Speedgoat^® FPGA I/O modules. This setting requires Xilinx^® Vivado^® and uses the same infrastructure as the IP Core Generation setting. For more information, see Simulink Real-Time FPGA I/O: Speedgoat Target Computer.

FPGA Turnkey

Deploy your Simulink model onto standalone FPGA boards and SoC platforms. To use this setting, you must set Language to VHDL. This setting requires the HDL Workflow Advisor. When you select this option, you can select from one of the hardware platforms listed in FPGA Turnkey Hardware.

Note

This option will be deprecated in a future release.

Customization for USRP™ Device

This workflow requires the HDL Workflow Advisor.

Note

This option will be deprecated in a future release.

Command-Line Information

Property: Workflow

Type: character vector

Value: 'Generic ASIC/FPGA' |

'IP Core
                            Generation'

| 'FPGA-in-the-Loop' | 'Simulink Real-Time FPGA I/O' | 'Customization for USRP Device'

Default: 'Generic ASIC/FPGA'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Project Folder

Specify a folder for workflow-specific files. Any created files are placed in this folder, such as the generated IP core or synthesis tool project files. The generated HDL code is placed in the directory specified by Folder.

If the Project Folder is empty, HDL Coder™ generates the files in the current directory. When Project Folder is set to a new value, the Code Generation Folder parameter updates to <ProjectFolder>/hdlsrc, so that the generated HDL code and workflow files generate in the same top-level directory. If you prefer to keep your generated HDL code in a separate directory, you can update the Code Generation Folder value after changing Project Folder.

Settings

Default: ''

The default project folder is your working folder.

Command-Line Information

Property: ProjectFolder

Type: character vector

Value: A valid path to your project folder

Default: ''

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to store generated files and folders into a custom project folder for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','ProjectFolder','C:/Temp/hdlprj')

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ProjectFolder','C:/Temp/hdlprj')
makehdl('sfir_fixed/symmetric_fir')
```