Target Language and Folder Selection Parameters

This page describes configuration parameters in the HDL Code Generation pane of the Configuration Parameters dialog box. By using these parameters, you can specify the Subsystem that you want to generate HDL code for, the target HDL language, and the target folder into which code is generated.

Generate HDL for

Select the subsystem or model from which code is generated. The list includes the path to the root model and to subsystems in the model. When you specify this parameter and click the Generate button, HDL Coder™ generates code for the Subsystem that you specify. By default, the HDL code is generated in VHDL language and into the hdlsrc folder.

Settings

Default: The top level subsystem in the root model is selected.

Command-Line Information

Property: HDLSubsystem

Type: character vector

Value: A valid path to your subsystem

Default: Path to the top level subsystem in root model

For example, you can generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Specify the subsystem using the property HDLSubsystem as an argument to makehdl.
```
makehdl('sfir_fixed','HDLSubsystem','sfir_fixed/symmetric_fir')
```
Pass in the path to the subsystem as an first argument to makehdl.
```
makehdl('sfir_fixed/symmetric_fir')
```

Language

Select the language (VHDL^®, Verilog^®, or SystemVerilog ) in which code is generated. The selected language is referred to as the target language. When you specify the Language and click the Generate button, HDL Coder generates code in that language for the Subsystem that is specified by the Generate HDL for parameter. By default, the HDL code is generated in VHDL language and into the hdlsrc folder.

The generated HDL code complies with these standards:

VHDL-1993 (IEEE^® 1076-1993)
Verilog-2001 (IEEE 1364-2001)
SystemVerilog-2005 (IEEE 1800-2005)

Settings

Default: VHDL

VHDL: Generate VHDL code.
Verilog: Generate Verilog code.
SystemVerilog: Generate SystemVerilog code.

Command-Line Information

Property: TargetLanguage

Type: character vector

Value: 'VHDL' | 'Verilog' | 'SystemVerilog'

Default: 'VHDL'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to generate Verilog code for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','TargetLanguage','Verilog')
makehdl('sfir_fixed/symmetric_fir')
```

Code Generation Folder

Enter a path to the folder into which code is generated. Alternatively, click Browse to navigate to and select a folder. The selected folder is referred to as the target folder. When you specify the Code Generation Folder and click the Generate button, HDL Coder generates code into that folder for the Subsystem that is specified by the Generate HDL for parameter. By default, the HDL code is generated in VHDL language and into the hdlsrc folder.

Settings

Default: The default target folder is a subfolder of your working folder, named hdlsrc. HDL Coder writes the generated files into this subfolder. The folder name can be a complete path name, specified as a character vector.

Command-Line Information

Property: TargetDirectory

Type: character vector

Value: A valid path to your target folder

Default: 'hdlsrc'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to generate HDL code into a custom target folder for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','TargetDirectory','C:/Temp/hdlsrc')

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','TargetDirectory','C:/Temp/hdlsrc')
makehdl('sfir_fixed/symmetric_fir')
```

Restore Model Defaults

This button resets the model-level HDL settings to the default values. The block settings are not changed. To clear the block settings, use hdlrestoreparams.

Note

If you clear the model-level settings, you cannot restore the previous settings. To restore the settings, close the model without saving and then reopen the model.

Command-Line Information

Function: hdlrestoreparams

Type: character vector

Value: model name

Default: ''

Run Compatibility Checker

This setting checks whether the Subsystem that you specify by using Generate HDL for is compatible for HDL code generation. The setting generates a HDL Check Report that displays errors, warnings, and messages. See Check Subsystem for HDL Compatibility.

Command-Line Information

Function: checkhdl

Type: character vector

Value: subsystem or model name

Default: ''

Generate

This setting generates HDL code for the Subsystem that you specify by using Generate HDL for. If the Subsystem is not HDL-compatible, the code generator displays errors in the HDL Check Report.

Command-Line Information

Function: makehdl

Type: character vector

Value: subsystem or model name

Default: ''