Main Content

Test Bench Stimulus and Output Parameters

This page describes configuration parameters that reside in the HDL Code Generation > Test Bench tab of the Configuration Parameters dialog box. Using the parameters in this tab, you can specify whether to ignore data checking, and hold input data between samples.

Hold input data between samples

Specify how long subrate signal values are held in valid state.

Settings

Default: On

On

Data values for subrate signals are held in a valid state across N base-rate clock cycles, where N is the number of base-rate clock cycles that elapse per subrate sample period. (N >= 2.)

Off

Data values for subrate signals are held in a valid state for only one base-rate clock cycle. For the subsequent base-rate cycles, data is in an unknown state (expressed as 'X') until leading edge of the next subrate sample period.

Tip

In most cases, the default (On) is the best setting for Hold input data between samples. This setting matches the behavior of a Simulink® simulation, in which subrate signals are held valid through each base-rate clock period.

In some cases (for example modeling memory or memory interfaces), it is desirable to clear Hold input data between samples. In this way you can obtain diagnostic information about when data is in an invalid ('X') state.

Dependency

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: HoldInputDataBetweenSamples
Type: character vector
Value: 'on' | 'off'
Default: 'on'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
            'HoldInputDataBetweenSamples', 'off')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'HoldInputDataBetweenSamples', 'off')
makehdltb('sfir_fixed/symmetric_fir')

Initialize test bench inputs

Specify initial value driven on test bench inputs before data is asserted to DUT.

Settings

Default: Off

On

Initial value driven on test bench inputs is'0'.

Off

Initial value driven on test bench inputs is 'X' (unknown).

Dependency

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: InitializeTestBenchInputs
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
            'InitializeTestBenchInputs', 'on')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'InitializeTestBenchInputs', 'on')
makehdltb('sfir_fixed/symmetric_fir')

Ignore output data checking (number of samples)

Specify number of samples during which output data checking is suppressed.

Settings

Default: 0

The value must be a nonnegative integer.

When the value of Ignore output data checking (number of samples), N, is greater than zero, the test bench suppresses output data checking for the first N output samples after the clock enable output (ce_out) is asserted.

When using pipelined block implementations, output data may be in an invalid state for some number of samples. To avoid spurious test bench errors, determine this number and set Ignore output data checking (number of samples) accordingly.

Be careful to specify N as a number of samples, not as a number of clock cycles. For a single-rate model, these are equivalent, but they are not equivalent for a multirate model.

You should use Ignore output data checking (number of samples) in cases where there is a state (register) initial condition in the HDL code that does not match the Simulink state, including the following specific cases:

  • When you set the DistributedPipelining property to 'on' for the MATLAB Function block (see Use Distributed Pipelining Optimization in Models with MATLAB Function Blocks)

  • When you set the ResetType property to 'None' for the following blocks:

    • commcnvintrlv2/Convolutional Deinterleaver

    • commcnvintrlv2/Convolutional Interleaver

    • commcnvintrlv2/General Multiplexed Deinterleaver

    • commcnvintrlv2/General Multiplexed Interleaver

    • dspsigops/Delay

    • simulink/Additional Math & Discrete/Additional Discrete/Unit Delay Enabled

    • simulink/Commonly Used Blocks/Unit Delay

    • simulink/Discrete/Delay

    • simulink/Discrete/Memory

    • simulink/Discrete/Tapped Delay

    • simulink/User-Defined Functions/MATLAB Function

    • sflib/Chart

    • sflib/Truth Table

  • When generating a black box interface to existing manually written HDL code

Dependency

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: IgnoreDataChecking
Type: integer
Default: 0

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
            'IgnoreDataChecking', 2)

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'IgnoreDataChecking', 2)
makehdltb('sfir_fixed/symmetric_fir')

Use file I/O to read/write test bench data

Create and use data files for reading and writing test bench input and output data.

Settings

Default: On

On

Create and use data files for reading and writing test bench input and output data.

Off

Use constants in the test bench for DUT stimulus and reference data.

Dependency

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: UseFileIOInTestBench
Type: character vector
Value: 'on' | 'off'
Default: 'on'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
            'UseFileIOInTestBench', 'off')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'UseFileIOInTestBench', 'off')
makehdltb('sfir_fixed/symmetric_fir')