Generate HDL and HLS Code from a Timing Offset Estimation Algorithm

R2026b

This example shows how to generate HDL and HLS code from a MATLAB^® function that implements a lead-lag timing offset estimation algorithm for wireless communication receivers.

In wireless communication systems, the receiver oversamples incoming data at the RF front end. The timing offset estimation algorithm determines where to sample the received waveform so that the receiver captures data near the maximum amplitude point. This example implements a recursive lead-lag estimator that operates at the symbol rate (once every oversampling period) and outputs a continuously updated timing offset estimate.

Examine the MATLAB Design and Test Bench

Set up the MATLAB function and test bench for this example. In the MATLAB Command Window, enter:

mlhdlc_demo_setup("mlhdlc_comms_toe");

This command opens a temporary working folder with the files required to run this example. The folder includes these files:

• MATLAB function

• Test bench

• <model>_runme.m script, which includes the commands to generate HLS code

The MATLAB function, mlhdlc_comms_toe, accepts a vector of oversampled received signal values and a smoothing factor as inputs. It stores the input vector in a persistent buffer and computes a lead-lag offset error from neighboring samples around the current timing estimate. The function recursively updates the timing offset and outputs the updated estimate and the sampled symbol value.

To view the function, enter:

open mlhdlc_comms_toe.m;

The test bench file, mlhdlc_comms_toe_tb, verifies the behavior of the MATLAB function. It generates a binary phase-shift keying (BPSK) signal oversampled at 8 samples per symbol and adds white noise. It then applies a pulse-shaping filter with a deliberate timing offset and streams symbol-rate vectors through the design. The test bench plots the received signal with time-correct detections and the estimated timing offset over time. To view the test bench, enter:

open mlhdlc_comms_toe_tb;

Simulate the Design

To check for run-time errors, simulate the design by running the test bench. In the MATLAB Command Window, enter:

mlhdlc_comms_toe_tb;

Generate HDL Code

To generate HDL code, create a fixed-point configuration object and an HDL configuration object by using the coder.config function. Associate the test bench with both configuration objects.

Specify the MATLAB function and test bench, then create the configuration objects.

designName = "mlhdlc_comms_toe";
designTB = "mlhdlc_comms_toe_tb";
fixptCfg = coder.config("fixpt");
fixptCfg.TestBenchName = designTB;
cfg = coder.config("hdl");
cfg.TestBenchName = designTB;

Specify the synthesis tool, chip family, device name, package name, and speed value:

cfg.SynthesisTool = "Xilinx Vivado";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

Generate code:

codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName, ...
"-launchreport");

After code generation completes, the report opens. Examine the generated HDL code in the report.

Generate HLS Code

The mlhdlc_comms_toe_runme script specifies the target files, enables the settings required for this example, and generates HLS code.

The script specifies the MATLAB function and test bench, then creates a fixed-point configuration object by using the coder.config function. It associates the test bench with the configuration object.

designName = "mlhdlc_comms_toe";
designTB = "mlhdlc_comms_toe_tb";
fixptCfg = coder.config("fixpt");
fixptCfg.TestBenchName = designTB;

The script creates an HLS configuration object by using the coder.config function, associates the test bench, and enables simulation.

cfg = coder.config("hls");
cfg.TestBenchName = designTB;
cfg.GenerateHLSTestBench = true;
cfg.SimulateGeneratedCode = true;

The script generates code:

codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName, ...
"-launchreport");

Run the Script

First, modify the mlhdlc_comms_toe_runme script. The script disables synthesis by default. Set the SynthesizeGeneratedCode property to true:

cfg.SynthesizeGeneratedCode = true;

Depending on your synthesis tool, set one of these flags to true:

isCodingForStratusHLS = false;
isCodingForVitisHLS = true;

Depending on your synthesis tool, update these settings:

if isCodingForStratusHLS
    cfg.SynthesisTool = "Cadence Stratus HLS";
elseif isCodingForVitisHLS
    cfg.SynthesisTool = "Xilinx Vitis HLS";
    cfg.SynthesisToolChipFamily = "Artix7";
    cfg.SynthesisToolDeviceName = "xa7a100t";
    cfg.SynthesisToolPackageName = "csg324";
    cfg.SynthesisToolSpeedValue = "-1I";
end

Generate code by running the script:

mlhdlc_comms_toe_runme

After code generation completes, the report opens. Examine the generated HLS code in the report.