Stop simulation when input is nonzero
Simulink / Sinks
HDL Coder / Sinks
The Stop Simulation block stops the simulation when the input is nonzero. The simulation completes the current time step before terminating. If the block input is a vector, any nonzero vector element causes the simulation to stop.
When you use the Stop Simulation block in a For Iterator subsystem, the stop action occurs after execution of all iterations in the subsystem during a time step. The stop action does not interrupt execution until the start of the next time step.
You cannot use the Stop Simulation block to pause the simulation. To create a block that pauses the simulation, see Pause Simulation Using Assertion Blocks.
Port_1 — Input signal
scalar | vector | matrix
Stop simulation when input signal is nonzero. This port accepts real
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Not recommended for production code. Relates to resource limits and restrictions on speed and memory often found in embedded systems. Generated code can contain dynamic allocation and freeing of memory, recursion, additional memory overhead, and widely varying execution times. While the code is functionally valid and acceptable in resource-rich environments, smaller embedded targets often cannot support such code. Usually, blocks evolve toward being suitable for production code. Thus, blocks suitable for production code remain suitable.
Generated code stops executing when the stop condition is true.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
This block can be used to stop simulation when used with subsystems that generates code, but is not included in the hardware implementation.
PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.
Introduced before R2006a