If you have an existing model, subsystem, or subchart in Simulink®, configure portions of your design for Simulink Design Verifier™ analysis. Use the bottom-up approach, analyzing smaller components first, for best results with a large or complex model. If you are just beginning your design process, see Design Considerations.
Overview of the basic Simulink Design Verifier workflow.
Describes how to check whether your model is compatible with Simulink Design Verifier.
How to use automatic stubbing.
Explains how subsystems and atomic subcharts are extracted for individual analysis.
Analyze an individual subsystem.
Analyzing an atomic subchart using Simulink Design Verifier software.
Analyzing a simple example model with Simulink Design Verifier.
Describes techniques for analyzing a large model.
This example shows how to compile an S-Function to be compatible with Simulink® Design Verifier™ for test case generation.
Explains the benefits of analyzing a model starting with low-level elements.
Specify analysis options and configure Simulink Design Verifier output.
Overview of the Simulink Design Verifier options in the Configuration Parameters dialog box.
Accessing the Simulink Design Verifier block library.
Lists Simulink software features that Simulink Design Verifier does not support.
Lists Simulink blocks that Simulink Design Verifier does and does not support.
Simulink Design Verifier supports the Model block with some limitations.
Lists the Stateflow® software features that the Simulink Design Verifier and Fixed-Point Designer™ software does not support.
Lists limitations associated with Simulink Design Verifier software support for MATLAB® for code generation.
Describes limitations and considerations of S-functions and Generated Code in Simulink Design Verifier.