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Extend Test Cases for Model with Temporal Logic

Create Starting Test Case

This example uses the sldvdemo_sbr_extend_design model. This model includes a Stateflow® chart SBR that uses temporal logic. The transition from the KEY_OFF state to the KEY_ON state occurs after the Stateflow chart has been simulated 500 times. To test this transition requires a test case with 500 time steps.

In this example, you create a test case that forces the transition to KEY_ON by setting the KEY input to 1 for the duration of the test case. You simulate the model using this test case, satisfying the objectives for the KEY_OFF/KEY_ON transition. Then you analyze the model, ignoring the objectives already satisfied by the test case you create.

  1. Open the example model:

  2. Open the SBR Stateflow chart to see the KEY_OFF/KEY_ON transition.

  3. Create a model reference harness model:

    [~, harnessModelFilePath] = ...
        sldvmakeharness('sldvdemo_sbr_extend_design',[],[],true);

    The harness model, sldvdemo_sbr_extend_design_harness, includes:

    • A Model block named Test Unit that references the original model, sldvdemo_sbr_extend_design.

    • A Signal Builder block named Inputs that contains the test-case inputs to the model referenced in the Model block.

      Initially, the Signal Builder block contains only the default test case, with all three inputs set to 0.

    • A DocBlock block named Test Case Explanation that documents the test case.

      Initially, the Test Case Explanation block does not have any content for the default test case.

  4. sldvmakeharness returns the path to the harness model file in harnessModelFilePath. Extract the name of the harness model file into harnessModel, for later use:

    [~, harnessModel] = fileparts(harnessModelFilePath);

In order to analyze the KEY_OFF to KEY_ON state transition, create a test case that makes the transition to the KEY_ON state in 500 time steps:

  1. Open the Signal Builder dialog box for the harness model.

  2. Select Axes > Change Time Range.

  3. The Signal Builder's time range determines the span of time over which its output is explicitly defined. In the Set the total time range dialog box, set the Max time field to 5 seconds, creating 500 time steps of 0.01 seconds duration each.

  4. Set the KEY input to 1 for the duration of this starting test case, forcing the transition to the KEY_ON state. Selecting the Inputs.KEY signal requires two clicks. First, click the signal so that dots appear at both ends of the signal.

  5. Click the Inputs.KEY signal again. The Signal Builder thickens the signal to indicate that it is selected.

  6. At the bottom of the Signal Builder dialog box, under Left Point, enter 1 for Y.

  7. Press Enter to apply the change.

    The Inputs.KEY signal is set to 1 for the duration of the test case.

  8. Close the Signal Builder dialog box.

Log Starting Test Case

The next step is to log the starting test case that you created. You can then specify that Simulink® Design Verifier™ ignore the objectives satisfied by that test case when performing an analysis.

The sldvlogsignals function records the test case data in a MAT-file that contains an sldvData structure. This structure stores all the data that the software gathers and produces during the analysis.

To log the starting test cases:

  1. Save the name of the Model block in the harness model that references the sldvdemo_sbr_extend_design model:

    [~, modelBlock] = find_mdlrefs(harnessModel, false);
  2. Simulate the model referenced by the Model block using the new test case, and log the input signals in the workspace variable loggeddata:

    loggeddata = sldvlogsignals(modelBlock{1});
  3. Save the logged data in a MAT-file named existingtestcase.mat:

    save('existingtestcase.mat', 'loggeddata');

    You will specify this file when you analyze the sldvdemo_sbr_extend_design model.

Extend Existing Test Cases

You can now analyze the sldvdemo_sbr_extend_design model and specify that the analysis extend the test cases already satisfied. The analysis uses the existing test-case data as a starting point, and does not try to generate test cases for the KEY_OFF to KEY_ON transition in the SBR Stateflow chart.

Specify the starting test case and analyze the model:

  1. Open the model.

    open_system('sldvdemo_sbr_extend_design');

  2. On the Design Verifier tab, click Test Generation Settings.

  3. In the Configuration Parameters dialog box, on the Test Generation pane, under Existing test cases, select Extend existing test cases.

  4. In the Data file field, enter the name of the MAT-file that contains the logged data:

    existingtestcase.mat
  5. Clear Ignore objectives satisfied by existing test cases.

    When you clear this option, the software includes the starting test case in the final test suite. You will see that the complete test suite achieves 100% model coverage.

  6. To close the Configuration Parameters dialog box, click OK.

  7. Save the sldvdemo_sbr_extend_design model on the MATLAB® path with the name sldvdemo_sbr_extend_design_test.

  8. Click Generate Tests.

    The log window first lists the objectives that the starting test case satisfied.

    The log window then lists the objectives generated beyond the starting test case.

Verify Analysis Results

To make sure that this analysis creates a complete test suite, generate the harness model so you can simulate the model with the generated test cases:

  1. On the Design Verifier tab, in the Review Results section, click Create Test Harness Model.

  2. In the harness model sldvdemo_sbr_extend_design_test_harness, open the Signal Builder block named Inputs.

  3. To simulate the model using all the test cases, click the Run all and produce coverage button .

    When the simulation is complete, the model coverage report is displayed.

  4. View the coverage information for the sldvdemo_sbr_extend_design_test model to see that the complete test suite achieves 100% coverage.

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