When creating a model, you can specify minimum and maximum values on input ports to mimic environmental constraints as part of your design. The Simulink® Design Verifier™ analysis can automatically consider these values as constraints for:
Design error detection
Test case generation
Specifying minimum and maximum input values is similar to using the Test Condition block to constrain signals for test case generation or the Proof Assumption block to constrain signals for property proving. The Test Condition and Proof Assumption blocks capture the analysis constraints. The Simulink Design Verifier software can also consider the design constraints captured in the Inport block minimum and maximum parameters as constraints for analysis.
For more information about signal values, see Investigate Signal Values.
By default, Simulink Design Verifier considers any minimum and maximum input values specified for Inport blocks in your model. To enable this capability:
On the Design Verifier tab, in the Prepare section, from the drop-down menu for the mode settings, click Settings.
In the Configuration Parameters dialog box, on the Design Verifier pane, select the Use specified input minimum and maximum values parameter.
After the analysis completes, to view the design minimum and maximum constraints for your model, click Generate detailed analysis reports.
The constraints are listed in the Analysis Information chapter of the Simulink Design Verifier report.
Simulink Design Verifier support for specified minimum and maximum values has the following limitations:
The analysis considers specified minimum and maximum values on root-level Inport blocks only. The analysis ignores minimum and maximum values specified on other Simulink blocks.