Register configuration clock frequency (MHz)

Registers system configuration clock frequency

Model Configuration Pane: Target hardware resources / FPGA design (top-level)

Description

The system configuration clock drives the configuration register interfaces for the vendor IP cores in the system. User-authored Simulink^® IP cores will utilize the parameter below for its configuration register bus.

Settings

50 (default)

Default: 50

Programmatic Use

Parameter:

Type:

Values: 50

Default: 50

Version History

Introduced in R2019a