Support for Fixed Reference Design
This workflow enables algorithm and system designers to generate an HDL IP core and integrate it into a fixed reference design for rapid prototyping. Create an SoC model based on the selected reference design for the supported Xilinx® Versal devices by using the SoC Model Creator tool. Use the created model as a template to design and simulate your FPGA algorithm and processor algorithm. Then, generate a bitstream, build a software application, and program the board by using the SoC Builder tool.
|SoC Model Creator
|Create SoC model based on selected reference design (Since R2021b)