Documentation

Custom IP Core Generation

Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board.

HDL Coder™ can generate a custom HDL IP core that you can deploy to the Intel® FPGA boards. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you register for the board.

Topics

Custom IP Core Generation (HDL Coder)

Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.

Custom IP Core Report (HDL Coder)

You generate an HTML custom IP core report by default when you generate a custom IP core.

Featured Examples

Save Target Hardware Settings in Model

Save Target Hardware Settings in Model

Save your target hardware settings in a Simulink® model.

Open Script
HDL Coder Support Package for Intel FPGA Boards Documentation
Support
Deploying LTE Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow

Deploying LTE Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow

Download white paper