Supported EDA Tools and Hardware

Software

Microchip Libero SoC

Use this support package with these recommended versions:

• Microchip Libero^® SoC v12.0

For tool setup instructions, see Software Setup.

Software Setup

To use the Libero tool suite with HDL Verifier™ FPGA-in-the-loop (FIL), you must first add the FIL IP to Libero SoC Mega Vault.

Software Setup with an Internet Connection

To add the FIL IP to Libero SoC using an internet connection, follow these steps:

1. Launch Libero SoC.

2. From the Libero SoC menu, select View > Windows > Catalog to open the Catalog pane.

3. Click the Download them now! button to start downloading.

   The IP catalog list now includes Solution-FIL-HSP-IP.

   

4. Close Libero SoC.

5. Launch MATLAB^®.

6. Set hdlsetuptoolpath to point to the Libero SoC installation. For example:

   hdlsetuptoolpath('ToolName','Microchip Libero SoC',...
      'ToolPath','C:\Microsemi\Libero_SoC_v12.0\Designer\bin\libero.exe')

Software Setup Without Internet Connection

To add the FIL IP to Libero SoC with no internet connection, follow these steps:

1. On a machine with internet connection, navigate to the Libero SoC Downloads page.

2. Download the desired version of Mega Vault, and copy it to a portable storage device (such as a USB drive).

3. Connect the storage device to the target machine, copy the Mega Vault file to the local machine, then unzip this file.

4. Launch Libero SoC.

5. From the Libero SoC menu, select Project > Vault/Repositories Settings > Vault location. Set the path to the Mega Vault location.

   

6. Close Libero SoC.

7. Launch MATLAB.

8. Set hdlsetuptoolpath to point to the Libero SoC installation. For example:

   hdlsetuptoolpath('ToolName','Microchip Libero SoC',...
      'ToolPath','C:\Microsemi\Libero_SoC_v12.0\Designer\bin\libero.exe')

Note

When setting up for RTG4^® without an internet connection, you must install Mega Vault v12.3 if using Libero v12.0 or newer.

Required IP Cores for FPGA-in-the-Loop

Installing Microchip Mega-Vault, enables access to the required IP cores for FIL simulation. You can choose to download only the required IP cores.

• Microchip SmartFusion^®2 requires Microsemi:SolutionCore:idu_top

• Microchip Polarfire^® requires:

  • Actel:SgCore:PF_CCC

  • Microsemi:SolutionCore:iog_cdr_test_wrapper

• RTG4 requires:

  • Actel:SgCore:RTG4FCCC

  • Microsemi:SolutionCore:CM1_TOP

Board Connections

Ethernet Connection

You can run FPGA-in-the-loop over an Ethernet connection.

Required Hardware	Supported Interfaces	Required Software
Gigabit Ethernet card Cross-over Ethernet cable FPGA board with supported Ethernet connection	Gigabit Ethernet — SGMII	There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication.

Related Topics

• FPGA-in-the-Loop Simulation
• FPGA-in-the-Loop Simulation Workflows