This example shows how GPU Coder™ Support Package for NVIDIA® GPUs enables the GPU Coder product to run PIL execution on NVIDIA® DRIVE™ and Jetson hardware platforms. A fog rectification example is used to demonstrate this feature. For more information on fog rectification function, see GPU Code generation for fog rectification.
Target Board Requirements
NVIDIA Jetson TX1/TX2 embedded platform.
Ethernet crossover cable to connect the target board and host PC (if the target board cannot be connected to a local network).
NVIDIA CUDA toolkit installed on the board.
Environment variables on the target for the compilers and libraries. For information on the supported versions of the compilers and libraries and their setup, see installing and setting up prerequisites for NVIDIA boards.
Development Host Requirements
GPU Coder for code generation. For an overview and tutorials visit the GPU Coder product page.
Embedded Coder™ for code generation. For an overview and tutorials, visit the Embedded Coder product page.
NVIDIA CUDA toolkit on the host.
Environment variables on the host for the compilers and libraries. For information on the supported versions of the compilers and libraries, see Third-party Products. For setting up the environment variables, see Environment Variables.
The following line of code creates a folder in your current working directory (host), and copies all the relevant files into this folder. If you cannot generate files in this folder, change your current working directory before running this command.
The GPU Coder Support Package for NVIDIA GPUs uses an SSH connection over TCP/IP to execute commands while building and running the generated CUDA code on the DRIVE or Jetson platforms. You must therefore connect the target platform to the same network as the host computer or use an Ethernet crossover cable to connect the board directly to the host computer. Refer to the NVIDIA documentation on how to set up and configure your board.
To communicate with the NVIDIA hardware, you must create a live hardware connection object by using the drive or jetson function. You must know the host name or IP address, username, and password of the target board to create a live hardware connection object. For example, use the following command to create live object for Jetson hardware,
hwobj = jetson('jetson-tx2-name','ubuntu','ubuntu');
Similarly, use the following command to create live object for DRIVE hardware,
hwobj = drive('drive-px2-name','ubuntu','ubuntu');
Use the coder.checkGpuInstall function and verify that the compilers and libraries needed for running this example are set up correctly.
envCfg = coder.gpuEnvConfig('jetson'); % Use 'drive' for NVIDIA DRIVE hardware envCfg.BasicCodegen = 1; envCfg.Quiet = 1; envCfg.HardwareObject = hwobj; coder.checkGpuInstall(envCfg);
To run PIL execution NVIDIA target, create a GPU code configuration object for 'lib' and set verification mode to 'PIL'.
cfg = coder.gpuConfig('lib'); cfg.VerificationMode = 'PIL';
Use the coder.hardware function to create a configuration object for the DRIVE or Jetson platform and assign it to the
Hardware property of the code configuration object
'NVIDIA Jetson' for the Jetson TX1 or TX2 boards and
'NVIDIA Drive' for the DRIVE board.
cfg.Hardware = coder.hardware('NVIDIA Jetson');
To enable code execution profiling, set
CodeExecutionProfiling of the GPU Coder configuration object to true.
cfg.CodeExecutionProfiling = true;
Load foggy input image.
foggyImg = imread('foggyInput.png');
To generate CUDA code, use the codegen function and pass the GPU code configuration along with the size of the inputs for
fog_rectification entry-point function. It creates a
MEX function named
fog_rectification_pil for PIL-based execution.
fog_rectification_pil MEX function with required input to run the code on the target and get results into the MATLAB.
defoggyImg_pil = fog_rectification_pil(foggyImg);
p1 = subplot(1, 2, 1); p2 = subplot(1, 2, 2); imshow(foggyImg, 'Parent', p1); imshow(defoggyImg_pil, 'Parent', p2); title(p1, 'Foggy Input Image'); title(p2, 'Defogged Output Image from Hardware');
To verify the numerical accuracy of the generated code, compare MATLAB results with those from the PIL execution.
defoggyImg_sim = fog_rectification(foggyImg); diffImg = defoggyImg_sim - defoggyImg_pil; fprintf('The maximum difference between the PIL output and Simulation output is %f', max(diffImg(:)));
The profiling results are available after clearing the PIL MEX function.
Configure the report generator and bring up the profiling report, where
TimerTicksPerSecond holds the target hardware clock frequency.
executionProfile=getCoderExecutionProfile('fog_rectification'); executionProfile.TimerTicksPerSecond = 2035 * 1e6; report(executionProfile, ... 'Units', 'Seconds', ... 'ScaleFactor', '1e-03', ... 'NumericFormat', '%0.3f');
Remove the files and return to the original folder.