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C280x/C2802x/C2803x/C2805x/C2806x/C2833x/C2834x/F28M3x/F2807x/F2837xD/F2837xS/F28004x ePWM

Generate enhanced Pulse Width Modulated (ePWM) waveforms

Library

Embedded Coder® Support Package for Texas Instruments™ C2000™ Processors/ C2802x

Embedded Coder Support Package for Texas Instruments C2000 Processors/ C2803x

Embedded Coder Support Package for Texas Instruments C2000 Processors/ C2805x

Embedded Coder Support Package for Texas Instruments C2000 Processors/ C2806x

Embedded Coder Support Package for Texas Instruments C2000 Processors/ C280x

Embedded Coder Support Package for Texas Instruments C2000 Processors/ C2833x

Embedded Coder Support Package for Texas Instruments C2000 Processors/ C2834x

Embedded Coder Support Package for Texas Instruments C2000 Processors/ F2807x

Embedded Coder Support Package for Texas Instruments C2000 Processors/ F2837xD

Embedded Coder Support Package for Texas Instruments C2000 Processors/ F2837xS

Embedded Coder Support Package for Texas Instruments C2000 Processors/ F28004x

Embedded Coder Support Package for Texas Instruments C2000 F28M3x Concerto™ Processors/ F28M35x/ C28x

Embedded Coder Support Package for Texas Instruments C2000 F28M3x Concerto Processors/ F28M36x/ C28x

Description

Use this block to generate ePWM waveforms. Multiple ePWM modules are available on C28x devices. Each module has two outputs, ePWMA and ePWMB.

When you enable the High-Resolution Pulse Width Modulator (HRPWM), the ePWM block uses the Scale Factor Optimizing (SFO) software library . The SFO library can “dynamically determine the number of MEP steps per SYSCLKOUT period.” For more information, consult TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide, Literature Number SPRU924, available at the Texas Instruments Web site.

This block is common to various C28x devices. Some parameters may appear or disappear depending on which library the block is taken from. The blue label on the top right corner of the block displays the family that will be used to show parameters. As the block is a superset of functionalities available on different devices, some parameter selection maybe meaningless.

Parameters

General Pane

Allow use of 16 HRPWMs (for C28044) instead of 6 PWMs

Enable all 16 High-Resolution PWM modules (HRPWM) on the C28044 digital signal controller when the PWM resolution is too low.

For example, the Spectrum Digital eZdsp™ F28044 board has a system clock of 100 MHz (200-kHz switching). At these frequencies, conventional PWM resolution is too low—approximately 9 bits or 10 bits. By comparison, the HRPWM resolution for the same board is 14.8 bits.

All the ePWM blocks in your model become HRPWM blocks, Thus, when you enable this parameter:

  • Use the HRPWM parameters under the ePWMA tab to make additional configuration changes.

  • Most of the configuration parameters under the ePWMB tab are unavailable.

  • Your model can contain up to 16 C280x/C2803x/C2833x ePWM blocks, provided you configure each one for a separate module. (For example, Module is ePWM1, ePWM2, and so on.)

For processors other than the C28044, deselect (disable) Allow use of 16 HRPWMs (for C28044) instead of 6 PWMs. To enable HRPWM for other processors, first determine how many HRPWM modules are available. Consult the Texas Instruments documentation for your processor, and then use the HRPWM parameters under the ePWMA tab to enable and configure HRPWM.

Module

Specify which ePWM module to use.

ePWMLink TBPRD

Select an ePWM module to which you want to link the current ePWM module for timer period. When you link timer period of an ePWM module with another, the Timer period value of the linked ePWM module is used in the current module. The Timer period units, Specify timer period via and the Timer period parameters do not appear when you select another ePWM module for linking.

However, the linking has no effect when you link an ePWM module to a module that does not exist in your model. This parameter is available only with some of the TI’s C2000™ processors.

Timer period units

Specify the units of the Timer period or Timer initial period as Clock cycles (the default) or Seconds. When Timer period units is set to Seconds, the software converts the Timer period or Timer initial period from a value in seconds to a value in clock cycles. For best results, select Clock cycles. Doing so reduces calculations and rounding errors.

Note

If you set Timer period units to Seconds, enable support for floating-point numbers. In the model window, select Simulation > Model Configuration Parameters.

In the Configuration Parameters dialog box, select Code Generation > Interface. Under Software Environment, enable floating-point numbers.

Specify timer period via

Configure the source of the timer period value. When you set this parameter to the Input port option, the Timer period parameter changes to Timer initial period and creates a timer period input port, T, on the block.

Timer period

Set the period of the ePWM counter waveform. The resultant ePWM waveform period depends on the settings of the Action when counter= parameters in the ePWMx tab.

When you enable HRPWM, you can enter a high-precision floating point value. The time-base period high resolution register (TBPRDHR) stores the high-resolution portion of the timer period value.

The timer period is calculated based on the Counting mode selection and Timer period units, as shown:

Count ModeTimer period unitsCalculationExample
Up or DownClock cycles

The value entered in clock cycles is used to calculate the time-base period (TBPRD) for the ePWM timer register. The period of the ePWM timer, TCTR = (TBPRD + 1) * TBCLK. Where, TCTR is the timer period in seconds, and TBCLK is the time-base clock.

For EPWMCLK frequency = 200 MHz, TBCLK = 5 ns.

Note

EPWMCLK will be equal to SYSCLKOUT or SYSCLKOUT/2 depending on the EPWM clock divider (EPWMCLKDIV) parameter setting.

When the timer period is entered in clock cycles, TBPRD = 9999, and the ePWM timer period is calculated as, TCTR = 50 µs.

For the default action settings in the ePWMx tab, the ePWM period = 50 µs.

Seconds

The value entered in seconds is used to calculate the time-base period (TBPRD) for the ePWM timer register. The TBPRD value entered in the register, TBPRD = (TCTR / TBCLK) – 1. Where, TCTR is the timer period in seconds, and TBCLK is the time-base clock.

For the default action settings in the ePWMx tab, the ePWM period is the same as the timer period (in seconds) entered.

For EPWMCLK frequency = 200 MHz, TBCLK = 5 ns.

When the timer period is entered in seconds, TBPRD = 9999, and the ePWM timer period is calculated as, TCTR = 50 µs.

For the default action settings in the ePWMx tab, the ePWM period = 50 µs.

Up-DownClock cycles

The value entered in clock cycles is used to calculate the time-base period (TBPRD) for the ePWM timer register. The period of the ePWM timer, TCTR = 2 * TBPRD * TBCLK. Where, TCTR is the timer period in seconds, and TBCLK is the time-base clock.

For EPWMCLK frequency = 200 MHz, TBCLK = 5 ns.

When the timer period is entered in clock cycles, TBPRD = 10000, and the ePWM timer period is calculated as, TCTR = 100 µs.

For the default action settings in the ePWMx tab, the ePWM period = 100 µs.

Seconds

The value entered in seconds is used to calculate the time-base period (TBPRD) for the ePWM timer register. The TBPRD value entered in the register, TBPRD = TCTR / TBCLK. Where, TCTR is the timer period in seconds, and TBCLK is the time-base clock.

For the default action settings in the ePWMx tab, the ePWM period is two times the timer period (in seconds) entered.

For EPWMCLK frequency = 200 MHz, TBCLK = 5 ns.

When the timer period is entered in seconds, TBPRD = 10000, and the ePWM timer period is calculated as, TCTR = 50 µs.

For the default action settings in the ePWMx tab, the ePWM period = 100 µs.

Timer initial period

The initial period of the waveform from the time the PWM peripheral starts operation until the ePWM input port, T, receives a new value for the period. Use Timer period units to measure the period in clock cycles or in seconds. The timer period is calculated similar to the Timer period parameter.

This parameter appears only when you set the Specify timer period via parmeter to the Input port option.

Reload for time base period register (PRDLD)

The time at which the counter period is reset.

  • Counter equals to zero The counter period refreshes when the value of the counter is 0.

  • Immediate without using shadow The counter period refreshes immediately.

Counting mode

Specify the counting mode in which to operate. This PWM module can operate in three distinct counting modes: Up, Down, and Up-Down. The Down option is not compatible with HRPWM. To avoid an error when you build the model, do not set the Counting mode parameter to Down and select the Enable HRPWM (Period) parameter checkbox.

The following illustration shows the waveforms that correspond to these three modes:

Synchronization action

Specify the source of a phase offset to apply to the Time-base synchronization input signal, EPWMxSYNCI from the SYNC input port. Selecting Set counter to phase value specified via dialog creates the Phase offset value parameter. Selecting Set counter to phase value specified via input port creates a phase input port, PHS, on the block. Selecting Disable, the default value prevents the application of phase offsets to the TB module.

Counting direction after phase synchronization

This parameter appears when Counting mode is Up-Down and Synchronization action is Set counter to phase value specified via dialog or Input port. Configure the timer to count up or down, following synchronization. This parameter corresponds to the PHSDIR field of the Time-base Control Register (TBCTL).

Phase offset value (TBPHS)

This field appears when you select Set counter to phase value specified via dialog in Synchronization action.

The offset value will be loaded in the Time Base Counter on a Synchronization event.

Note

Enter the Phase offset value (TBPHS) in TBCLK cycles, from 0 to 65535. While using HRPWM, you may enter decimal values.

This parameter corresponds to the Time-Base Phase Register (TBPHS).

Specify software synchronization via input port (SWFSYNC)

Create an input port, SYNC, for a Time-base synchronization input signal, EPWMxSYNCI. You can use this option to achieve precise synchronization across multiple ePWM modules by daisy-chaining multiple Time-base (TB) submodules.

Enable digital compare A event1 synchronization (DCAEVT1)

This parameter only appears for specific C28x devices.

Synchronize the ePWM time base to a DCAEVT1 digital compare event. Use this feature to synchronize this PWM module to the time base of another PWM module. Fine-tune the synchronization between the two modules using the Phase offset value. This option is not compatible with HRPWM. Enabling HRPWM disables this option.

Enable digital compare B event1 synchronization (DCBEVT1)

This parameter only appears for specific C28x devices.

Synchronize the ePWM time base to a DCBEVT1 digital compare event. Use this feature to synchronize this PWM module to the time base of another PWM module. Fine-tune the synchronization between the two modules using the Phase offset value. This option is not compatible with HRPWM. Enabling HRPWM disables this option.

Synchronization output (SYNCO)

This parameter corresponds to the SYNCOSEL field in the Time-Base Control Register (TBCTL).

Use this parameter to specify the event that generates a Time-base synchronization output signal, EPWMxSYNCO, from the Time-base (TB) submodule.

The available choices are:

  • Pass through (EPWMxSYNCI or SWFSYNC) — a Synchronization input pulse or Software forced synchronization pulse, respectively. You can use this option to achieve precise synchronization across multiple ePWM modules by daisy chaining multiple Time-base (TB) submodules.

  • Counter equals to zero (CTR=Zero) — Time-base counter equal to zero (TBCTR = 0x0000)

  • Counter equals to compare B (CTR=CMPB) — Time-base counter equal to counter-compare B (TBCTR = CMPB)

  • Disable — Disable the EPWMxSYNCO output (the default)

Time base clock (TBCLK) prescaler divider

Use the Time base clock (TBCLK) prescaler divider (CLKDIV) and the High speed time base clock (HSPCLKDIV) prescaler divider (HSPCLKDIV) to configure the Time-base clock speed (TBCLK) for the ePWM module. Calculate TBCLK using the following equation:

TBCLK in Hz = PWM clock in Hz/(HSPCLKDIV * CLKDIV)

For example, the default values of both CLKDIV and HSPCLKDIV are 1, and the default frequency of PWM clock is 100 MHz, so:

TBCLK in Hz = 100 MHz/(1 * 1) = 100 MHz

TBCLK in seconds = 1/TBCLK in Hz = 1/100 MHz = 0.01 µs

The choices for the Time base clock (TBCLK) prescaler divider are: 1, 2, 4, 8, 16, 32, 64, and 128.

The Time block clock (TBCLK) prescaler divider parameter corresponds to the CLKDIV field of the Time-base Control Register (TBCTL).

Note

The PWM clock is the SYSCLKOUT or a clock derived from SYSCLKOUT using the PWM Clock divider. For a few TI C2000 processors, there may be a PWM clock divider that divides the SYSCLKOUT to derive the PWM module clock. Check your processor’s technical reference manual to know more details.

The frequency of SYSCLKOUT depends on the oscillator frequency and the configuration of PLL-based clock module. Changing the value of SYSCLOCKOUT affects the timing of all ePWM modules. If there is a PWM clock prescale available in the processor, changing its value also affects the PWM timing.

High speed time base clock (HSPCLKDIV) prescaler divider

See the Time base clock (TBCLK) prescaler divider topic for an explanation of the role of this value in setting the speed of the Time-base Clock. Choices are to divide by 1, 2, 4, 6, 8, 10, 12, and 14. Selecting Enable high resolution PWM (HRPWM – period) forces this option to 1.

This parameter corresponds to the HSPCLKDIV field of the Time-base Control Register (TBCTL).

Enable swap module A and B

This parameter only appears for specific C28x devices.

Swap the ePWMA and ePWMB outputs. This option outputs the ePWMA signals on the ePWMB outputs and the ePWMB signals on the ePWMA outputs.

ePWMA and ePWMB panes

Each ePWM module has two outputs, ePWMA and ePWMB. The ePWMA output pane and ePWMB output pane include the same settings, although the default values vary in some cases, as noted.

Enable ePWM#x

Enables the ePWMA and/or ePWMB output signals for the ePWM module selected on the General pane. In this case, # represents the ePWM module and x represents A or B. By default, Enable ePWM#A is enabled, and Enable ePWM#B is disabled.

Note

When you select Enable ePWM#A or Enable ePWM#B, enable support for floating-point numbers by browsing to Configuration Parameters > Code Generation > Interface > Software Environment.

CMPx initial value

This field appears when you set CMPx source to Input port. In this case, x represents A or B. Enter the initial pulse width of CMPA or CMPB that the PWM peripheral uses when it starts operation. Subsequent inputs to the WA or WB ports change the CMPA or CMPB pulse width.

Action when counter=ZERO, Action when counter=period (PRD), Action when counter=CMPA on up-count (CAU), Action when counter=CMPA on down-count (CAD), Action when counter=CMPB on up-count (CBU), Action when counter=CMPB on down-count (CBD)

These settings along with the other remaining settings in the ePWMA output and ePWMB output panes, determine the behavior of the Action Qualifier (AQ) submodule. The AQ module determines which events are converted into various action types, producing the required switched waveforms of the ePWM#A and ePWM#B output signals.

For each of these four fields, the available choices are Do nothing, Clear, Set, and Toggle.

The default values for these fields vary between the ePWMA output and ePWMB output panes.

The following table shows the defaults for each of these panes when you set Counting mode to Up or Up-Down:

Action when counter =...ePWMA output paneePWMB output pane
ZEROSetClear
period (PRD)ClearSet
CMPA on up-count (CAU)ClearSet
CMPA on down-count (CAD)SetDo nothing
CMPB on up-count (CBU)Do nothingClear
CMPB on down-count (CBD)Do nothingSet

The following table shows the defaults for each of these panes when you set Counting mode to Down:

Action when counter =...ePWMA output paneePWMB output pane
ZERODo nothingDo nothing
period (PRD)ClearClear
CMPA on down-count (CAD)SetDo nothing
CMPB on down-count (CBD)Do nothingSet

For a detailed discussion of the AQ submodule, consult the TMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (SPRU791), available on the Texas Instruments Web site.

Compare value reload condition, Add continuous software force input port, Continuous software force logic, Reload condition for software force

These four settings determine how the action-qualifier (AQ) submodule handles the S/W force event, an asynchronous event initiated by software (CPU) via control register bits.

Compare value reload condition determines if and when to reload the Action-qualifier S/W Force Register from a shadow register. Choices are Load on counter equals to zero (CTR=Zero) (the default), Load on counter equals to period (CTR=PRD), Load on either, and Freeze.

Add continuous software force input port creates an input port, SFA, which you can use to control the software force logic. Send one of the following values to SFA as an unsigned integer data type:

  • 0 = Forcing disable: Do nothing. The default option.

  • 1 = Forcing low: Clear low

  • 2 = Forcing high: Set high

If you did not create the SFA input port, you can use Continuous software force logic to select which type of software force logic to apply. The choices are:

  • Forcing disable: Do nothing. The default.

  • Forcing low: Clear low

  • Forcing high: Set high

Reload condition for software force — Choices are Zero (the default), Period, Either period or zero, and Immediate.

Inverted version of ePWM#A

This parameter only appears for specific C28x devices.

Invert the ePWM#A signal and output it on the ePWM#B outputs.

This parameter sets the SELOUTB field in the HRPWM Configuration Register (HRCNFG).

Enable high resolution PWM (HRPWM)

This parameter appears at this position in the C280x and C2833x ePWM blocks.

Select to enable High Resolution PWM settings. When the effective resolution for conventionally generated PWM is insufficient, consider High Resolution PWM (HRPWM). The resolution of PWM is normally dependent upon the PWM frequency and the underlying system clock frequency. To address this limitation, HRPWM uses Micro Edge Positioner (MEP) technology to position edges more finely by dividing each coarse system clock. The accuracy of the subdivision is on the order of 150ps. The following figure shows the relationship between one system clock and edge position in terms of MEP steps:

High resolution PWM (HRPWM) loading mode

This parameter appears at this position in the C280x and C2833x ePWM blocks.

Determine when to transfer the value of the CMPAHR shadow to the active register:

  • Counter equals to zero (CTR=ZERO): Transfer the value when the time base counter equals zero (TBCTR = 0x0000).

  • Counter equals to period (CTR=PRD): Transfer the value when the time base counter equals the period (TBCTR = TBPRD).

  • CTR=Zero or CTR=PRD Transfer the value when either case is true.

High resolution PWM (HRPWM) control mode

This parameter appears at this position in the C280x and C2833x ePWM blocks.

Select which register controls the Micro Edge Positioner (MEP) step size. The High resolution PWM (HRPWM) control mode option configures the CTLMODE “Control Mode Bits”.

  • Duty control mode uses the Extension Register for HRPWM Duty (CMPAHR) or the Extension Register for HRPWM Period (TBPRDHR) to control the MEP edge position.

  • Select Phase control mode to use the Time Base Period High-Resolution Register (TBPRDHR) to control the MEP edge position.

The High resolution PWM (HRPWM) control mode option configures the CTLMODE “Control Mode Bits” in the HRPWM Configuration Register (HRCNFG).

High resolution (HRPWM) edge control mode

This parameter appears at this position in the C280x and C2833x ePWM blocks.

Swap the ePWMA and ePWMB outputs. This parameter sets the SWAPAB field in the HRPWM Configuration Register (HRCNFG).

Use scale factor optimizer (SFO) software

Enable scale factor optimizing (SFO) software with HRPWM. This software dynamically determines the scaling factor for the Micro Edge Positioner (MEP) step size. The step size varies depending on operating conditions such as temperature and voltage. The SFO software reduces variability due to these conditions. For more information, see the “Scale Factor Optimizing Software (SFO)” section of the TMS320x2802x, 2803x Piccolo High Resolution Pulse Width Modulator (HRPWM) Reference Guide, Literature Number: SPRUGE8.

Counter Compare Pane

The four compare registers—CMPA, CMPB, CMPC, and CMPD, are compared with the time-base counter value to generate appropriate events. CMPA and CMPB events are used for controlling PWM duty cycle by selecting appropriate actions in ePWMA and ePWMB panes. These events can also be used to generate an interrupt to the CPU and/or a start of conversion pulse to the ADC. You can refer to the Event Trigger pane to select the events to be triggered.

ePWMLink CMPx

Select an ePWM module to which you want to link the current ePWM module for counter value. In this case, x represents A, B, C, or D. When you link counter value of an ePWM module with another, the CMPx value value of the linked ePWM module is used in the current module. The CMPx, Specify CMPx via, and CMPx value parameters do not appear when you select another ePWM module for linking.

However, the linking has no effect when you link an ePWM module to a module that does not exist in your model. This parameter is available only with some of the TI’s C2000 processors.

CMPx units

Specify the units used by the compare register: Percentages (the default) or Clock cycles. In this case, x represents A, B, C, or D.

Notes

  • The term clock cycles refers to the time-base clock on the processor. See the TB clock prescaler divider topic for an explanation of time-base clock speed calculations.

  • Percentages use additional computation time in generated code and can decrease accuracy of the results.

  • If you set CMPx units to Percentages, enable support for floating-point numbers by browsing to Configuration Parameters > Code Generation > Interface > Software Environment.

Specify CMPx via

Specify the source of the pulse width. If you select Specify via dialog (the default), enter a value for the CMPx value parameter. If you select Input port, set the value using the input port, Wx on the block. If you select Input port, make sure to set the CMPx initial value parameter. In this case, x represents A, B, C, or D.

CMPx value

This field appears when you set CMPx source to Specify via dialog. Enter a value that specifies the pulse width, in the units specified in CMPx units. In this case, x represents A, B, C, or D.

Reload for compare x Register (SHDWxMODE)

The time at which the counter period is reset. In this case, x represents A, B, C, or D.

  • Counter equals to zero — refreshes the counter period when the value of the counter is 0.

  • Immediate without using shadow — refreshes the counter period immediately.

Deadband Unit Pane

The Deadband unit pane lets you specify parameters for the Dead-Band Generator (DB) submodule.

Use deadband for ePWM#A, Use deadband for ePWM#B

Enables a deadband area of Rising Edge Delay or Falling Edge Delay cycles without signal overlap between pairs of ePWM output signals. This check box is cleared by default.

Enable half-cycle clocking

This parameter only appears for specific C28x devices.

To double the deadband resolution, enable half-cycle clocking. This option clocks the deadband counters at TBCLK*2. When you disable this option, the deadband counters use full-cycle clocking (TBCLK*1).

Deadband polarity

Configure the deadband polarity as Active high (AH) (the default option), Active low (AL) , Active high complementary (AHC) or Active low complementary (ALC). During the Deadband time, both the ePWMA and ePWMB outputs have to set to an inactive state. Depending on your hardware settings, the inactive states can correspond to a high or a low logic value. Active high means that the system is active when the ePWM output is set to a high logic value. Active low means that the system is active when the ePWM output is set to a low logic value. Use the Complementary option when the B signal needs to be the inverse of A. For more information, refer to the ePWM Technical Reference guide of your processor.

Signal source for rising edge (RED)

Select the signal source to which rising edge delay (RED) has to be applied. By default ePWM#A signal is selected.

Signal source for falling edge (FED)

Select the signal source to which falling edge delay (FED) has to be applied. By default ePWM#A signal is selected.

Deadband period source

Specify the source of the control logic. Choose Specify via dialog (the default) to enter explicit values, or Input port to use a value from the input port.

Deadband Rising edge (RED) deadband period (0~16383)

The value you enter in the field specifies the dead band delay in time-base clock (TBCLK) cycles.

Deadband Falling edge (FED) deadband period (0~16383)

The value you enter in the field specifies the dead band delay in time-base clock (TBCLK) cycles.

Event Trigger Pane

Configure ADC Start of Conversion (SOC) by one or both of the ePWMA and ePWMB outputs.

Enable ADC start of conversion for module A

When you select this option, ADC Start of Conversion Event (ePWMSOCxA) is generated when the event selected in the Start of conversion for module A event selection parameter occurs.

Number of event for start of conversion for Module A (SOCA) to be generated

When you select Enable ADC start of conversion for module A, this field specifies the number of the event that triggers ADC Start of Conversion for Module A (SOCA): First event triggers ADC start of conversion with every event (the default). Second event triggers ADC start of conversion with every second event. Third event triggers ADC start of conversion with every third event.

Start of conversion for module A event selection

When you select Enable ADC start of conversion for module A, this field specifies the counter match condition that triggers an ADC start of conversion event. The choices are:

Digital Compare Module A Event 1 start of conversion (DCAEVT1.soc) and Digital Compare Module B Event 1 start of conversion (DCBEVT1.soc) (For specific C28x devices only)

When the ePWM asserts a DCAEVT1 or DCBEVT1 digital compare event. Use this feature to synchronize the selected PWM module to the time base of another PWM module. Fine-tune the synchronization between the two modules using the Phase offset value.

Counter equals to zero (CTR=Zero)

When the ePWM counter reaches zero (the default).

Counter equals to period (CTR=PRD)

When the ePWM counter reaches the period value.

Counter equals to zero or period (CTR=Zero or CTR=PRD)

When the time base counter reaches zero (TBCTR = 0x0000) or when the time base counter reaches the period (TBCTR = TBPRD).

Counter is incrementing and equals to the compare x register (CTRU=CMPx)

The ePWM counter reaches the compare value x on the way up. In this case, x represents A, B, C, or D.

Counter is decrementing and equals to the compare x register (CTRD=CMPx)

The ePWM counter reaches the compare value x on the way down. In this case, x represents A, B, C, or D.

Enable ADC start of conversion for module B

When you select this option, ADC Start of Conversion Event (ePWMSOCxB) is generated when the event selected in the Start of conversion for module B event selection parameter occurs.

Number of event for start of conversion for Module B (SOCB) to be generated

When you select Enable ADC start module B, this field specifies the number of the event that triggers ADC start of conversion: First event triggers ADC start of conversion with every event (the default), Second event triggers ADC start of conversion with every second event, and Third event triggers ADC start of conversion with every third event.

Start of conversion for module B event selection

When you select Enable ADC start of conversion for module B, this field specifies the counter match condition that triggers an ADC start of conversion event. The choices are the same as for Module A counter match event condition.

Enable ePWM interrupt

Select this option to generate interrupts based on different events defined by Number of event for interrupt to be generated and Interrupt counter match event condition. By default, the software clears (disables) this option.

Number of event for interrupt to be generated

When you select Enable ePWM interrupt, this field specifies the number of the event that triggers the ePWM interrupt: First event triggers ePWM interrupt with every event (the default), Second event triggers ePWM interrupt with every second event, and Third event triggers ePWM interrupt with every third event.

Interrupt counter match event condition

When you select Enable ePWM interrupt, this field specifies the counter match condition that triggers ePWM interrupt. The choices are the same as for Module A counter match event condition.

HRPWM Pane

Enable high resolution period on ePWM#A (HRPWM - period), Enable high resolution period on ePWM#B (HRPWM - period)

This parameter only appears for specific C28x devices.

When the effective resolution for conventionally generated PWM is insufficient, consider using High Resolution PWM (HRPWM). The resolution of PWM is normally dependent upon the PWM frequency and the underlying system clock frequency. To address this limitation, HRPWM uses Micro Edge Positioner (MEP) technology to position edges more finely by dividing each coarse system clock. The accuracy of the subdivision is on the order of 150ps. The following figure shows the relationship between one system clock and edge position in terms of MEP steps:

When this parameter is enabled, decimal values will be accepted for the timer period of the ePWM Module. The Extension Register for the HRPWM Period (TBPRDHR) provides an 8 bit representation of the decimal part of the Timer period value. This parameter enables the Enable high resolution PWM (HRPWM - duty) option, and displays the HRPWM loading mode, HRPWM control mode, and HRPWM edge control mode options. Also configure HRPWM control mode.

Selecting Enable HRPWM (Period) forces TB clock prescaler divider and High Speed TB clock prescaler divider to 1. These settings match the HRPWM time base clock with the SYSCLKOUT frequency.

The Down option in the Counting mode parameter is not compatible with HRPWM. To avoid an error when you build the model, do not set the Counting mode parameter to Down and select the Enable HRPWM (Period) parameter checkbox.

Enable HRPWM Duty on ePWM#A(HRPWM - duty)

This parameter only appears for specific C28x devices.

When this parameter is enabled, decimal values will be accepted for the Compare A value (CMPA) of the ePWM Module. The Extension Register for the HRPWM Compare A (CMPAHR) provides an 8 bit representation of the decimal part of the Compare value.

This parameter also enables HRPWM control mode.

High resolution PWM (HRPWM) loading mode on ePWM#A

This parameter appears when Enable high resolution PWM (HRPWM - period) or Enable high resolution PWM (HRPWM - duty) is selected. Determine when to transfer the value of the CMPAHR shadow to the active register:

  • Counter equals to zero (CTR=ZERO) — transfers the value when the time base counter equals zero (TBCTR = 0x0000).

  • Counter equals to period (CTR=PRD) — transfers the value when the time base counter equals the period (TBCTR = TBPRD).

  • Counter equals to either zero or period (CTR=ZERO or CTR=PRD) — transfers the value when either case is true.

This option configures the HRLOAD “Shadow Mode Bit” in the HRPWM Configuration Register (HRCNFG).

High resolution PWM (HRPWM) control mode on ePWM#A

This parameter appears when Enable high resolution PWM (HRPWM - period) or Enable high resolution PWM (HRPWM - duty) is selected. Select which register controls the Micro Edge Positioner (MEP) step size. The High resolution PWM (HRPWM) Control mode option configures the CTLMODE “Control Mode Bits”.

  • Duty control mode — uses the Extension Register for HRPWM Duty (CMPAHR) or the Extension Register for HRPWM Period (TBPRDHR) to control the MEP edge position.

  • Phase control mode — uses the Time Base Phase High Resolution Register (TBPHSHR) to control the MEP edge position.

The High resolution PWM (HRPWM) control mode — configures the CTLMODE “Control Mode Bits” in the HRPWM Configuration Register (HRCNFG).

High resolution PWM (HRPWM) edge control mode

This parameter appears when Enable high resolution PWM (HRPWM - period) or Enable high resolution PWM (HRPWM - duty) is selected.

Select the register that controls the Micro Edge Positioner (MEP) step size.

  • Rising Edge — MEP control of rising edge

  • Falling Edge — MEP control of falling edge

  • Both Edge — MEP control of both edges

The High resolution PWM (HRPWM) Edge Control mode option configures the EDGMODE “Edge Mode Bits” in the HRPWM Configuration Register (HRCNFG).

Use scale factor optimizer (SFO) software

This parameter is enabled, if the Enable high resolution PWM (HRPWM - period) or Enable high resolution PWM (HRPWM - duty) is selected.

Enable scale factor optimizing (SFO) software with HRPWM. This software dynamically determines the scaling factor for the Micro Edge Positioner (MEP) step size. The step size varies depending on operating conditions such as temperature and voltage. The SFO software reduces variability due to these conditions. For more information, see the “Scale Factor Optimizing Software (SFO)” section of the TMS320x2802x, 2803x Piccolo High Resolution Pulse Width Modulator (HRPWM) Reference Guide, Literature Number: SPRUGE8.

Enable auto convert

This parameter only appears for specific C28x devices and if Enable high resolution PWM (HRPWM - period) or Enable high resolution PWM (HRPWM - duty) is selected.

Apply the scaling factor calculated by the SFO software to the controlling period or duty cycle. (Use the HRPWM duty mode to select controlling period or duty cycle.) This parameter sets the AUTOCONV field in the HRPWM Configuration Register (HRCNFG).

PWM Chopper Control Pane

The PWM chopper control pane lets you specify parameters for the PWM-Chopper (PC) submodule. The PC submodule uses a high-frequency carrier signal to modulate the PWM waveform generated by the AQ and DB modules.

Chopper module enable

Select to enable the chopper module. Use of the chopper module is optional, so this check box is cleared by default.

Chopper frequency divider

Set the prescaler value that determines the frequency of the chopper clock. The system clock speed is divided by this value to determine the chopper clock frequency. Choose an integer value from 1 to 8.

Chopper clock cycles width of first pulse

Choose an integer value from 1 to 16 to set the width of the first pulse. This feature provides a high-energy first pulse for a hard and fast power switch turn on.

Chopper pulse duty cycle

The duty cycles of the second and subsequent pulses are also programmable. The duty cycle can be varied in steps of 12.5% from 12.5% to 87.5%.

Trip Zone Unit Pane

The Trip Zone unit pane lets you specify parameters for the Trip-zone (TZ) submodule. Each ePWM module receives TZ signals from the GPIO MUX. The number of Trip zone signals are different for C28x processor families. These signals can be used to force the ePWM output into a specific state based on an event like an external fault. Use the settings in this pane to program the ePWM outputs to respond to external events.

Trip zone source

Specify the source of the control logic for the Trip Zone signals. Select Specify via dialog (the default) to enable specific Trip-zone signals in the block dialog. Choose Input port to enable specific Trip-zone signals using a block input port, TZSEL.

If you select Input port, use the following bit operation to determine the value of the 16-bit integer to send to the TZSEL input port:

TZSEL INPUT VALUE = (OSHT6*213 + OSHT5*212 + OSHT4*211 + OSHT3*210 + OSHT2*29 + OSHT1*28 + CBC6*25 + CBC5*24 + CBC4*23 + CBC3*22 + CBC2*21 + CBC1*20)

The software uses the higher 8 bits for the One shot TZ1-TZ6 (OSHT1–6) and the lower 8 bits for Cyclic TZ1-TZ6 (CBC1–6). You can set up a group of TZ sources (1~6), use a bit operation to combine them into an integer, and then feed the integer to TZSEL.

For example, to enable One Shot TZ6 (OSHT6) and One Shot TZ5 (OSHT5) as trip zone sources, set OSHT6 and OSHT5 to “1” and leave the remaining values as “0”.

TZSEL INPUT VALUE = (1*213 + 1*212 + 0*211 …)

TZSEL INPUT VALUE = (8192 + 4096 + 0 …)

TZSEL INPUT VALUE = 12288

When the block receives this value, it applies it to the TZSEL register as a binary value: 11000000000000.

For more information, see the ”Trip-Zone Submodule Control and Status Registers” section of the TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, Literature Number: SPRU791 on www.ti.com

Enable One-Shot Trip zone# (TZ#)

This option is only available when the Trip zone source is Specify via dialog. Select this check box to enable the corresponding Trip-zone signal in One-Shot Mode. In this mode, when the trip event is active, the software performs the corresponding action on the EPWM#A/B output immediately and latches the condition. You can unlatch the condition using software control.

Enable one-shot digital compare A event 1 (DCAEVT1), Enable one-shot digital compare B event 1 (DCBEVT1)

Select these check boxes to enable the corresponding event signal as a OST trip source for event 1. In this mode, if the digital compare A or digital compare B event 1 is active, the software performs the corresponding action on the EPWM1A/B output immediately and latches the condition. You can unlatch the condition using the software control. This parameter is available only for specific C28x processors.

Enable Cyclic Trip zone# (TZ#)

This option is only available when the Trip zone source is Specify via dialog. Select this check box to enable the corresponding Trip-zone signal in Cycle-by-Cycle Mode. In this mode, when the trip event is active, the software performs the corresponding action on the EPWM#A/B output immediately and latches the condition. In Cycle-by-Cycle Mode, the software automatically clears condition when the ePWM Counter reaches zero. Therefore, in Cycle-by-Cycle Mode, every ePWM cycle resets or clears the trip event.

Enable cyclic digital compare A event 2 (DCAEVT2), Enable cyclic digital compare B event 2 (DCBEVT2)

Select these check boxes to enable the corresponding event signal as a cyclic trip source for event 2. In this mode, if the digital compare A or digital compare B event 2 is active, the software performs the corresponding action on the EPWM2A/B output immediately and latches the condition. In Cycle-by-Cycle Mode, the software automatically clears condition when the ePWM Counter reaches zero. Therefore, in Cycle-by-Cycle Mode, every ePWM cycle resets or clears the trip event. This parameter is available only for specific C28x processors.

Enable Trip-zone One-Shot interrupt (OST)

Generate an interrupt when any of the enabled one shot (OST) triggering events occur.

Enable Trip-zone Cycle-by-Cycle interrupt (CBC)

Generate an interrupt when any of the enabled cyclic or cycle-by-cycle (CBC) triggering events occur.

Digital comparator output A/B event 1/2 interrupt enable (DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2)

These parameters are available only for specific C28x processors. Generate an interrupt when Digital Comparator Output A or Digital Comparator Output B for event 1 or 2 occurs.

ePWM#A forced (TZ) to, ePWM#B forced (TZ) to, ePWM#A forced (DCAEVT#) to, ePWM#B forced (DCBEVT#) to

These parameters decide the actions to take on the ePWM outputs upon a trip-zone condition. The software overrides and forces the ePWM#A and/or ePWM#B (TZ or DCAEVTx) output to one of the following states: No action (the default), High, Low, or Hi-Z (High Impedance).

Digital Compare

This pane is available only for specific C28x processors.

Use the Digital Compare pane to configure the Digital Compare (DC) submodule parameters.

Each digital compare (DC) submodule receives three TZ signals (TZ1 to TZ3) from the GPIO MUX, and three COMP signals from the COMP (For specific C28x devices only). These signals indicate fault or trip conditions that are external to the PWM submodule. Use the settings in this pane to output specific DC events in response to those external signals. These DC events feed directly into the Time-base, Trip-zone, and Event-trigger submodules.

For more information, see the “Digital Compare (DC) Submodule” section of the TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, Literature Number: SPRUGE9.

Source for digital compare A high signal (DCAH), Source for digital compare B high signal (DCBH)

If the TZ or COMP signal selected is true, DCAH/DCBH will be set to a high logic value. Use the DCAEVT# source select, DCBEVT# source select options to determine the impact of DCAH/DCBH on DCAEVT# and DCBEVT#.

Source for digital compare A low signal (DCAL), Source for digital compare B low signal (DCBL)

If the TZ or COMP signal selected is true, DCAL/DCBL will be set to a high logic value. Use the DCAEVT# source select, DCBEVT# source select options to determine the impact of DCAL/DCBL on DCAEVT# and DCBEVT#.

Digital compare output A event # selection (DCAEVT#), Digital Compare output B event # selection (DCBEVT#)

Qualify the signals that generate DC events, such as DCAEVT# or DCBEVT#. Select the states of Source for digital compare A high signal DCAH, Source for digital compare B high signal DCBH, Source for digital compare A low signal (DCAL), and Source for digital compare B low signal (DCBL) that generate the event. To disable this feature, choose the Event disabled option.

DCAEVT# source select, DCBEVT# source select

This parameter controls two separate aspects of triggering DC events:

  • Triggering filtered or unfiltered DC event. (Configures DCACTL[EVT1SRCSEL] or DCACTL[EVT2SRCSEL].)

  • Trigger the DC event synchronously or asynchronously. (Configures DCACTL[EVT1FRCSYNCSEL] or DCACTL[EVT2FRCSYNCSEL].)

Filtering

  • Options that begin with DCAEVT# with sync or DCAEVT# with async do not apply filtering to DC events. Qualified signals trigger DC events.

  • Options that begin with DCEVTFILT sync apply filtering to DC events. Qualified signals pass through filtering circuits before triggering DC events. This filtering is not configurable in the ePWM block. For more information, refer to the “Event Filtering” section of the TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, Literature Number: SPRUGE9.

Synchronizing

  • Options that end with async trigger DC events asynchronously. When the qualified or filtered signals exist, the DC submodule triggers the DC event immediately.

  • Options that end with sync trigger DC events synchronously. Once the qualified or filtered signals exist, the DC submodule triggers the DC event in sync with the TBCLK signal.

    Note

    The following fields appear when you select DCEVTFILT with sync or DCEVTFILT with async for the DCAEVTX source select or DCBEVTX source select.

    For more details about the following parameters, refer to the sections:TMS320x2806x Piccolo processor: 3.2.9.3.2 (Event Filtering) and Table 56 of Technical Reference Manual (SPRUH18C). TMS320x2802x/03x Piccolo processors : 2.9.3.2 (Event Filtering) and Table 56 of Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (SPRUGE9E) for TMS320x2802x and TMS320x2803x Piccolo processors.

Pulse select

The blanking window which filters out event occurrences on the signal while active, is aligned to either a CTR = PRD pulse or a CTR = 0 pulse.

Blanking window inverted

The option that allows you to Enable or Disable the Inverted Blanking window.

Blanking window offset

The number of TBCLK cycles required from the blanking window reference to the point when the blanking window is applied.

Blanking window width

The duration of the blanking window in terms of TBCLK.

Filter source select

The option that allows you to select a source for Filtering.

The available options are:

  • Filtered version of DCAEVT1 (DCAEVT1FILT)

  • Filtered version of DCAEVT2 (DCAEVT2FILT)

  • Filtered version of DCBEVT1 (DCBEVT1FILT)

  • Filtered version of DCBEVT2 (DCBEVT2FILT)

Enable counter capture

The option that allows you to Enable or Disable the time-base counter capture.

References

For more information, consult the following references, available at the Texas Instruments Web site:

  • TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, literature number SPRU791

  • TMS320x280x, 2801x, 2804x High Resolution Pulse Width Modulator Reference Guide, literature number SPRU924

  • TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide, literature number SPRUGE9

  • TMS320x2802x, 2803x Piccolo High Resolution Pulse Width Modulator (HRPWM) Reference Guide, literature number SPRUGE8

  • TMS320x2805x Piccolo Technical Reference Manual, literature number SPRUHE5

  • TMS320x2806x Piccolo Technical Reference Manual, literature number SPRUH18

  • TMS320x28M35x Concerto Technical Reference Manual, literature number SPRUH22

  • TMS320x28M36x Concerto Technical Reference Manual, literature number SPRUHE8

  • Using the ePWM Module for 0% - 100% Duty Cycle Control Application Report, literature number SPRU791

  • Configuring Source of Multiple ePWM Trip-Zone Events, literature number SPRAAR4

  • TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs Data Manual, literature number SPRS230

  • TMS320F28044 Digital Signal Processor Data Manual, literature number SPRS357

  • TMS320F28335/28334/28332 TMS320F28235/28234/28232 Digital Signal Controllers (DSCs) Data Manual, literature number SPRS439