C28x Hardware Interrupt

Interrupt Service Routine to handle hardware interrupt on C28x processors

Library

Embedded Coder® Support Package for Texas Instruments™ C2000™ Processors/ Scheduling

Description

Execution scheduling models based on timer interrupts do not meet the requirements of some real-time applications to respond to external events. The C28x Hardware Interrupt block addresses this problem by allowing asynchronous processing of interrupts triggered by events managed by other blocks in the C280x/C2833x DSP Chip Support Library.

When the C28x Hardware Interrupt block has an external interrupt selection, the selection enables interrupts on the selected general-purpose I/O pins. To configure these pins, see the Configuration Parameters > Hardware Implementation > Hardware board settings > Target hardware resources > External Interrupt pane. For more information, see Hardware Implementation Pane: Texas Instruments C2000 Processors.

Vectorized Output

The output of this block is a function call. The size of the function call line equals the number of interrupts the block is set to handle. Each interrupt is represented by four parameters shown on the dialog box of the block. These parameters are a set of four vectors of equal length. Each interrupt is represented by one element from each parameter (four elements total), one from the same position in each of these vectors.

Each interrupt is described by:

  • CPU interrupt numbers

  • Peripheral Interrupts Expansion (PIE) interrupt numbers

  • Task priorities

  • Preemption flags

So, one interrupt is described by a CPU interrupt number, a PIE interrupt number, a task priority, and a preemption flag.

The CPU and PIE interrupt numbers together uniquely specify a single interrupt for a single peripheral or peripheral module.

The following table lists the PIE and CPU interrupt numbers for the c28x processors F280x, F2802x, F2803x, F2805x, F2806x, F2833x, F28M35x, and F28M36x that support 12×8 interrupts. The row headers 1–12 represent the CPU values, and the column headers 1–8 represent the PIE values.

PIE and CPU Interrupt Numbers for F280x, F2802x, F2803x, F2805x, F2806x, F2833x, F28M35x, and F28M36x Processors

PIE ⇒12345678
CPU ⇓
1SEQ1INT (ADC) / ADCINT1SEQ2INT (ADC) / ADCINT2ReservedXINT1XINT2ADCINT / ADCINT9TINT0 (TIMER 0)WAKEINT (LPM/WD)
2EPWM1_TZINT EPWM2_TZINTEPWM3_TZINT EPWM4_TZINT EPWM5_TZINT EPWM6_ TZINT EPWM7_TZINT EPWM8_TZINT
3EPWM1_INTEPWM2_INTEPWM3_INTEPWM4_INTEPWM5_INTEPWM6_ INTEPWM7_INTEPWM8_INT
4ECAP1_INTECAP2_INTECAP3_INTECAP4_INTECAP5_INTECAP6_INTEPWM10_TZINT / HRCAP1_INTEPWM9_TZINT / HRCAP2_INT
5EQEP1_INTEQEP2_INTEQEP3_INTHRCAP3_INTHRCAP4_INTReservedEPWM10_INTEPWM9_INT
6SPIRXINTA (SPI-A)SPITXINTA (SPI-A)SPIRXINTB (SPIB_RX) / MRINTB (McBSP-B)SPITXINTB (SPIB_TX) / MXINTB (McBSP-B)SPIRXINTC (SPI-C) / MRINTA (McBSP-A_RX)SPITXINTC (SPI-C) / MXINTA (McBSP-A_TX)SPIRXINTD (SPI-D) / EPWM12_TZINTSPITXINTD (SPI-D) / EPWM11_TZINT
7DINTCH1 (DMA1)DINTCH2 (DMA2)DINTCH3 (DMA3)DINTCH4 (DMA4)DINTCH5 (DMA5)DINTCH6 (DMA6)EPWM12_INTEPWM11_INT
8I2CINT1AI2CINT2AReservedReservedSCIRXINTC (SCI-C)SCITXINTC (SCI-C)ReservedReserved
9SCIRXINTA (SCIA_RX)SCITXINTA (SCIA_TX)SCIRXINTB (SCIB_RX) / LINA_INT0SCITXINTB (SCIB_TX) / LINA_INT1ECAN0INTA (CANA_1)ECAN1INTA (CANA_2)ECAN0INTB (CANB_1)ECAN1INTB (CANB_2)
10EPWM9_TZINT / ADCINT1EPWM10_TZINT / ADCINT2EPWM11_TZINT / ADCINT3EPWM12_TZINT / ADCINT4EPWM13_TZINT / ADCINT5EPWM14_TZINT / ADCINT6EPWM15_TZINT / ADCINT7EPWM16_TZINT / ADCINT8
11CLA1_INT1 / EPWM9_INT7 / MTOCIPCINT1 CLA1_INT2 / EPWM10_INT / MTOCIPCINT2CLA1_INT3 / EPWM11_INT / MTOCIPCINT3 CLA1_INT4 / EPWM12_INT / MTOCIPCINT4 /CLA1_INT5 / EPWM13_INTCLA1_INT6 / EPWM14_INTCLA1_INT7 / EPWM15_INTCLA1_INT8 / EPWM16_INT
12XINT3XINT4 / C28FLSINGERRXINT5XINT6 / C28RAMSINGERRXINT7 / C28RAMACCVIOLReservedLVFLUF

The PIE and CPU interrupt numbers for the c28x processors F2807x, F2837xS, F2837xD, F2838x, and F28004x that support 12×16 interrupts are:

PIE and CPU Interrupt Numbers for F2807x, F2837xS, F2837xD, F2838x, and F28004x Processors

PIE ⇒12345678
CPU ⇓
1ADCA1ADCB1ADCC1XINT1XINT2ADCD1TIMER 0WAKE / WDOG
2EPWM1_TZ EPWM2_TZEPWM3_TZEPWM4_TZEPWM5_TZEPWM6_ TZEPWM7_TZEPWM8_TZ
3EPWM1EPWM2EPWM3EPWM4EPWM5EPWM6EPWM7EPWM8
4ECAP1ECAP2ECAP3ECAP4ECAP5ECAP6ECAP7Reserved
5EQEP1EQEP2EQEP3ReservedCLB1CLB2CLB3CLB4
6SPIA_RXSPIA_TXSPIB_RXSPIB_TXMCBSPA_RXMCBSPA_TXMCBSPB_RXMCBSPB_TX
7DMA_CH1DMA_CH2DMA_CH3DMA_CH4DMA_CH5DMA_CH6ReservedReserved
8I2CAI2CA_FIFOI2CBI2CB_FIFOSCIC_RXSCIC_TXSCID_RXSCID_TX
9SCIA_RXSCIA_TXSCIB_RXSCIB_TXCANA_0CANA_1CANB_0CANB_1
10ADCA_EVTADCA2ADCA3ADCA4ADCB_EVTADCB2ADCB3ADCB4
11CLA1_1 CLA1_2 CLA1_3 CLA1_4CLA1_5CLA1_6CLA1_7CLA1_8
12XINT3XINT4XINT5MPOSTFMC.DONEVCUFPU_OVERFLOWFPU_UNDERFLOW
PIE ⇒910111213141516
CPU ⇓
1I2CA

SYS_ERR

ECATSYNC0 (CPU1 only)ECATINTn (CPU1 only)IPC0/CIPC0 IPC1/CIPC1IPC2/CIPC2IPC3/CIPC3
2EPWM9_TZEPWM10_ TZEPWM11_TZEPWM12_TZEPWM13_TZEPWM14_TZEPWM15_TZEPWM16_TZ
3EPWM9 EPWM10EPWM11EPWM12EPWM13EPWM14EPWM15EPWM16
4FSITXA_INT1FSITXA_INT2FSITXB_INT1FSITXB_INT2FSIRXA_INT1FSIRXA_INT2FSIRXB_INT1FSIRXB_INT2
5SD1 / SDFM1SD2/SDFM1ECATRSTINTn (CPU1 only)ECATSYNC1 (CPU1 only)SDFM1DR1SDFM1DR2SDFM1DR3SDFM1DR4
6SPIC_RX SPIC_TXSPID_RXSPID_TXSDFM2DR1SDFM2DR2SDFM2DR3SDFM2DR4
7FSIRXC_INT1FSIRXC_INT2FSIRXD_INT1FSIRXD_INT2FSIRXE_INT1FSIRXE_INT2FSIRXF_INT1FSIRXF_INT2
8LINA_0/FSIRXG_INT1LINA_1/FSIRXG_INT2FSIRXH_INT1FSIRXH_INT2PMBUSA/CLB5CLB6UPPA (CPU1 only)/CLB7 CLB8
9MCANSS_INT0(CPU1 only)MCANSS_INT1 (CPU1 only)MCANSS_ECC_CORR_PUL_INT (CPU1 only)MCANSS_WAKE_AND_TS_PLS_INT (CPU1 only)PMBUSACM_STATUS (CPU1 only)USBA (CPU1 only)Reserved
10ADCC_EVTADCC2 ADCC3ADCC4ADCD_EVTADCD2ADCD3ADCD4
11CMTOCPUxIPCINTR0CMTOCPUxIPCINTR1CMTOCPUxIPCINTR2CMTOCPUxIPCINTR3CMTOCPUxIPCINTR4CMTOCPUxIPCINTR5CMTOCPUxIPCINTR6CMTOCPUxIPCINTR7
12EMIF_ ERRORRAM_CORRECTABLE_ERROR/ECAP6INT2 FLASH_CORRECTABLE_ERROR/ECAP7INT2 RAM_ACCESS_VIOLATIONSYS_PLL_ SLIP/CPUxCRC_INTAUX_PLL_SLIP//CLA1CRC_INTCLA OVER FLOWCLA UNDERFLOW

The PIE and CPU interrupt numbers for the c281x processors are:

PIE and CPU Interrupt Numbers for C281x Processors

PIE ⇒12345678
CPU ⇓
1PDPINTA (EV-A)PDPINTB (EV-B)ReservedXINT1XINT2ADCINT (ADC)TINT0 (TIMER 0)WAKEINT (LPM/WD)
2CMP1INT (EV-A)CMP2INT (EV-A)CMP3INT (EV-A)T1PINT (EV-A)T1CINT (EV-A)T1UFINT (EV-A)T1OFINT (EV-A)Reserved
3T2PINT (EV-A)T2CINT (EV-A)T2UFINT (EV-A)T2OFINT (EV-A)CAPINT1 (EV-A)CAPINT2 (EV-A)CAPINT3 (EV-A)Reserved
4CMP4INT (EV-B)CMP5INT (EV-B)CMP6INT (EV-B)T3PINT (EV-B)T3CINT (EV-B)T3UFINT (EV-B)T3OFINT (EV-B)Reserved
5T4PINT (EV-B)T4CINT (EV-B)T4UFINT (EV-B)T4OFINT (EV-B)CAPINT4 (EV-B)CAPINT5 (EV-B)CAPINT6 (EV-B)Reserved
6SPIRXINTA (SPI)SPITXINTA (SPI)ReservedReservedMRINT (McBSP)MXINT (McBSP)ReservedReserved
7ReservedReservedReservedReservedReservedReservedReservedReserved
8ReservedReservedReservedReservedReservedReservedReservedReserved
9SCIRXINTA (SCI-A)SCITXINTA (SCI-A)SCIRXINTB (SCI-B)SCITXINTB (SCI-B)ECAN0INT (CAN)ECAN1INT (CAN)ReservedReserved
10ReservedReservedReservedReservedReservedReservedReservedReserved
11ReservedReservedReservedReservedReservedReservedReservedReserved
12ReservedReservedReservedReservedReservedReservedReservedReserved

The task priority indicates the relative importance tasks associated with the asynchronous interrupts. If an interrupt triggers a higher-priority task while a lower-priority task is running, the execution of the lower-priority task is suspended while the higher-priority task is executed. The lowest value represents the highest priority. The default priority value of the base rate task is 40, so the priority value for each asynchronously triggered task must be less than 40 for these tasks to suspend the base rate task.

The preemption flag determines whether a given interrupt is pre-emptable. Preemption overrides prioritization, such that a preemptable task of higher priority can be preempted by a non-preemptable task of lower priority.

Parameters

CPU interrupt numbers

Enter a vector of CPU interrupt numbers for the interrupts you want to process asynchronously.

PIE interrupt numbers

Enter a vector of PIE interrupt numbers for the interrupts you want to process asynchronously.

Simulink task priorities

Enter a vector of task priorities for the interrupts you want to process asynchronously.

See the discussion of this block's Vectorized Output for an explanation of task priorities.

Preemption flags

Enter a vector of preemption flags for the interrupts you want to process asynchronously.

See the discussion of this block's Vectorized Output for an explanation of preemption flags.

Enable simulation input

Select this check box if you want to be able to test asynchronous interrupt processing in the context of your Simulink® software model.

Note

Select this check box to enable you to test asynchronous interrupt processing behavior in Simulink software.