The high-speed peripheral clock (HSPCLK) or the system clock (SYSCLKOUT) controls the internal timing of ADC modules. The ADC derives the operating clock speed from the HSPCLK/SYSCLKOUT speed in several prescaler stages. For more information about configuring these scalers, see Configuring Acquisition Window Width for ADC Blocks.
You can set the following parameters for the ADC clock prescaler:
This parameter is available only for the dual-core processor F2837xD with
the Build options > Select CPU parameter set to
The CPU core that controls the ADC module. When you select the
Auto option for the ADC_x module in a
model, the ADC_x module is assigned to the CPU1 core during code generation
if the ADC_x block is present in the model, else it is assigned to the CPU2
core. If an ADC_x module is assigned to a CPU core, you cannot use that
module in a model that runs in the other CPU core.
Select the ADCCLK divider. This is specific to a processor.
The clock frequency for ADC, which is auto generated based on the value you select in ADC clock prescaler (ADCCLK).
Enable or disable overlap of sample and conversion.
The HSPCLK is divided by ADCLKPS (a 4-bit value) as the first step in
deriving the core clock speed of the ADC. The default value is
After dividing the HSPCLK speed by the ADC clock prescaler
(ADCLKPS) value, divides the result by 2. The default value
The ADC module clock, which indicates the ADC operating clock speed.
This value determines the width of the sampling or acquisition period. The
higher the value, the wider is the sampling period. This value does not
directly alter the core clock speed of the ADC. The default value is
Acquisition window size determines the duration for which the sampling switch is closed. The width of SOC pulse is ADCTRL1[11:8] + 1 times the ADCLK period.
Refer to the individual TRM for specifying the ADC offset values.
By default, an internally generated band gap voltage reference supplies the ADC logic. However, depending on application requirements, you can enable the external reference so that the ADC logic uses an external voltage reference instead.
When the ADC generates an end of conversion (EOC) signal, an ADCINT# interrupt that indicates whether the previous interrupt flag has been acknowledged or not is generated.
The 280x ADC supports offset correction via a 9-bit value that it adds or
subtracts before the results are available in the ADC result registers.
Timing for results is not affected. The default value is
When you disable the Use external reference 2.048V or External reference option, the ADC logic uses a fixed 0–3.3 volt input range, and VREFHI and VREFLO are disabled. To interpret the ADC input as a ratiometric signal, select the External reference option. Then, set values for the high voltage reference (VREFHI) and the low voltage reference (VREFLO). VREFHI uses the external ADCINA0 pin, and VREFLO uses the internal GND.
Set the time when the ADC sets ADCINTFLG ADCINTx relative to the SOC and EOC pulses.
Enables SOC high priority mode. In
all in round robin
mode, the default selection, the ADC services each SOC
interrupt in a numerical sequence.
Choose one of the
high priority selections to
assign high priority to one or more of the SOCs. In this mode, the ADC
operates in round robin mode until it receives a high priority SOC
interrupt. The ADC finishes servicing the current SOC, services the high
priority SOCs, and then returns to the next SOC in the round robin
For example, the ADC is servicing SOC8 when it receives a high priority interrupt on SOC1. The ADC completes servicing SOC8, services SOC1, and then services SOC9.
The pin to which the ADC sends the XINT2SOC pulse.
The pin to which the ADC sends the ADCEXTSOC pulse. This parameter is available only for F2807x, F2837x processors.