This is machine translation

Translated by Microsoft
Mouseover text to see original. Click the button below to return to the English version of the page.

Note: This page has been translated by MathWorks. Click here to see
To view all translated materials including this page, select Country from the country navigator on the bottom of this page.

FPGA Data Capture

Capture signal data from live FPGA

Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB® or Simulink®. To capture the signals, HDL Verifier™ generates an IP core that you must integrate into your HDL project and deploy to the FPGA along with the rest of your design. HDL Verifier also generates an app, System object™, and Simulink model that communicate with the FPGA and return the data to MATLAB or Simulink.

To capture FPGA data:

  1. Generate customized components and an IP core. Specify port names and sizes for the generated IP. These ports connect to the signals you want to capture, and the signals you want to use as triggers to control when the capture occurs.

  2. Integrate the generated IP into your FPGA design and deploy the design to your FPGA board.

  3. Use the generated app, System object, or Simulink model to capture data for analysis, verification, or display. You can configure a trigger condition to control when the capture occurs.

See Data Capture Workflow.


FPGA Data Capture Component GeneratorConfigure and generate FPGA data capture components
FPGA Data CaptureCapture data from live FPGA into MATLAB workspace interactively


hdlverifier.FPGADataReaderCapture data from live FPGA into MATLAB workspace


FPGA Data ReaderCapture data from live FPGA into Simulink model


Data Capture Workflow

High-level steps for capturing signal data from a design running on an FPGA.


Use trigger conditions to capture data around specific events on the FPGA.

Design Considerations for Data Capture

Signal, timing, and JTAG limitations for FPGA data capture.

Featured Examples