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FPGA-in-the-Loop Simulation

Verification with FPGA hardware

Run a Simulink® or MATLAB® simulation that is synchronized with an HDL design running on a Xilinx® FPGA board.

Topics

FPGA-in-the-Loop Simulation (HDL Verifier)

FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.

FPGA-in-the-Loop Simulation Workflows (HDL Verifier)

Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.

Related Information

Featured Examples