HDL Coder™ can generate a custom HDL IP core that you can deploy to the Xilinx® FPGA boards. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you register for the board.
Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.
You generate an HTML custom IP core report by default when you generate a custom IP core.
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.