Zynq and FMCOMMS2/3/4 Transmitter Configuration
Libraries:
SoC Blockset Support Package for Xilinx Devices /
SDR /
AD9361
Description
The Zynq and FMCOMMS2/3/4 Transmitter Configuration block connects your hardware logic to the FMCOMMS2/3/4 radio transmitter hardware. In simulation, this block provides optional ports for center frequency and gain, which the SoC Builder tool maps to hardware pins. The block does not connect to the radio hardware from simulation.
Ports
Input
center frequency — External RF center frequency
nonnegative finite scalar
External RF center frequency, specified as a nonnegative finite scalar. The valid center frequency range is from 70 MHz to 6 GHz.
Dependencies
To enable this port, set the Source of center frequency
parameter to Input port
.
Data Types: double
gain — External gain
numeric scalar
External gain, specified as a numeric scalar. The valid gain range is –10 dB to 77 dB. The resolution is 0.25 dB.
Dependencies
To enable this port, set the Source of gain parameter to
Input port
.
Data Types: double
Parameters
Source of center frequency — Source of center frequency
Dialog
(default) | Input port
Source of center frequency, specified as one of these options:
Dialog
— Set the center frequency by using the Center frequency (Hz) parameter.Input port
— Set the center frequency by using the center frequency input port.
Center frequency (Hz) — RF center frequency
2.4e9
(default) | nonnegative scalar
RF center frequency, in Hz, specified as a nonnegative scalar. The valid range for center frequency is 70 MHz to 6 GHz.
Dependencies
To enable this parameter, set the Source of center frequency
to Dialog
.
Data Types: double
Source of gain — Source of gain
Dialog
(default) | Input port
Source of gain, specified as one of these options:
Dialog
— Specify the gain by using the Gain (dB) parameter.Input port
— Specify the gain by using the gain input port.
Gain (dB) — Gain
-10
(default) | numeric scalar
Gain, in dB, specified as a numeric scalar. The valid gain range is –10 dB to 77 dB. The resolution is 0.25 dB.
Dependencies
To enable this parameter, set Source of gain to
Dialog
.
Data Types: double
Baseband sample rate (Hz) — Baseband sampling rate
3840000
(default) | positive scalar
Baseband sampling rate, in Hz, specified as a positive scalar. The valid range of this parameter is 520.834 kHz to 61.44 MHz.
Data Types: double
Advanced
Data source select — Source of data
Host
(default) | DDS
Source of data, specified as one of these options:
Host
— Transmit the input of the AD9361 Tx block.DDS
— Enable the direct digital synthesizer (DDS) on the radio hardware to generate transmission data. The DDS generates two additive tones for two channels. To set the frequency and scale of the tones, use the DDS frequency (Hz), DDS phase (degrees*1000), and DDS scale parameters.
DDS frequency (Hz) — DDS tone frequencies
[1000000, 1000000; 1000000, 1000000]
(default) | 2-by-2 matrix
DDS tone frequencies, in Hz, specified as a 2-by-2 matrix. Each channel has two additive tones. Configure channel one in the first row and channel two in the second row. For each tone, the valid range is from 0 to Baseband sample rate (Hz)/2.
Dependencies
To enable this parameter, set Data source select to
DDS
.
Data Types: double
DDS phase (degrees*1000) — DDS tone phases
[0, 0; 0, 0]
(default) | 2-by-2 matrix
DDS tone phases, in degrees times 1000, specified as a 2-by-2 matrix. Each channel has two additive tones. Configure channel one in the first row and channel two in the second row. The valid range is from 0 to 359,999. Values are relative to the maximum tone phase shift of 360 degrees, where 359,999 is 359.999 degrees.
Dependencies
To enable this parameter, set Data source select to
DDS
.
Data Types: double
DDS scale — DDS tone scale factors
[250000, 250000; 250000, 250000 ]
(default) | 2-by-2 matrix
DDS tone scale factors, in millionths of full scale, specified as a 2-by-2 matrix. Each channel has two additive tones. Configure channel one in the first row and channel two in the second row. The valid range is –1e6 to 1e6. The values are relative to DAC output amplitude, where 1e6 is the maximum DAC output amplitude.
Dependencies
To enable this parameter, set Data source select to
DDS
.
Data Types: double
Extended Capabilities
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool.
Version History
Introduced in R2019a
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