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Deployment and Verification

Create bitstream containing user programming and download it to Xilinx® Zynq® Platform

HDL Coder™ can generate an IP core, integrate it into your EDK project, and program the Zynq hardware. Using Embedded Coder®, you can generate and build the embedded software, and run it on the ARM® processor.

Topics

Default System Reference Design

Learn about the default system reference design and using the reference design.

Default System with AXI4-Stream Interface Reference Design

Learn about how to use the default system with AXI4-Stream Interface reference design and its requirements.

Default Video System Reference Design

Learn about the default video system reference design and its requirements.

Default System with External DDR Memory Access Reference Design

Learn about the default system with external DDR3 memory access reference design and its requirements.

Related Information

Xilinx Zynq Platform (HDL Coder)

Featured Examples