Read data from IP core on Xilinx Zynq Platform
This block reads a data vector from a contiguous group of memory-mapped registers on an HDL Coder™ generated IP core. The AXI4-Interface Read block, using the central interconnect of the processing system, provides simple memory-mapped communication with the IP core on the FPGA. This block is best suited for low-throughput communication, such as inspecting status, state, or control registers. This diagram shows the path of the data before it reaches this block.
Port_1 — Data vector from IP core registers
The N-by-1 vector read from memory-mapped registers on the IP core, starting from the Register offset.
Device name — Path and name of IP core device
/dev/mwipcore (default) | character array
Enter the path and name of the IP core.
If you use HDL Coder to generate the IP core, HDL Coder maps the IP core to
Register offset — Offset of register from base address of IP core
hex2dec( '0104' ) (default) | decimal number character array
Enter the offset of the register from the base address of the IP core. The
block reads data from this register. Use the
hex2dec function when you
specify the address offset using a hexadecimal number character
Output vector size — Size of data vector to be read from IP core
1 (default) | positive integer
Enter the size of the data vector to be read from the IP core device.
Data type — Data type of IP core
uint16 (default) |
Select the data type used by the IP core.
Sample time — Sample time in seconds
0.001 (default) | positive scalar
The signal data output by the AXI4-Interface Read block polls directly from the IP core using AXI4-Lite protocol. The Sample time parameter value or the base-rate of the subsystem specifies the polling rate of the registers.
Introduced in R2013a