I am using Matlab HDL Coder to generate VHDL Code and want to add a "valid in/out" Port to my subsystems to ensure the timing in sequential operations on a macro level.
Valid in: Triggers the calculation of the subsystem with the current values of the subsytem input ports
Valid out: Signals (e.g. with an rising edge) that the calculation of the subsystem is finished
I have tinkered with several idears:
- Enabled subsystem with a state machine outside of the subsystem to control if the output values have changed
- A parallel path inside the subsystem which just routes the valid in directly to valid out - a rising edge is sourced when the calculation is started -> with "balenced delays" the valid out signal (should) rise when the calculation is ready
- some minor variations of the above / unsucessful approches
So , what is best practice when implementing a valid in / out control for a HDL Subsytem?