Can i use Simulink to cosimulate my implemented design?

Hi, I want to use Simulink to co-simulate in Modelsim my VHDL design, but I want it to be implemented.

I have used HDL cosimulation , and it works but I need the design to be implemented. Also, I have used FIL to test the design in hardware, but I wonder if I can use a block like I used to perform FPGA in the loop but using Modelsim.

Thanks a lot for your anwers.

Answer 1

[Kiran Kintali]

https://www.mathworks.com/products/hdl-verifier.html

Debug and Verify System Designs

Use system test benches and golden reference models in MATLAB and Simulink to verify that Verilog or VHDL code meets system specifications. Verify designs using MATLAB or Simulink with Cadence® Incisive® and Xcelium™ simulators, Mentor Graphics® ModelSim® and Questa® simulators, or the Xilinx® Vivado® simulator.

[Juan José Montes Salinero]

can I use Xilinx Vivado Simulator in cosimulation?

I thought that was not avaliable