errors due to simulation generation,black box unable for inherit sample time from system generator

Hi

I am implementing verilog code into simulink using system generator, I am using HDL Netlist compilation and using vivado simulator in black box and using matlab version R2016a and vivado version is 2017.2. I keep getting errors like

The S-function 'sysgen' in 'addii/Constant' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample time number 0. Inheriting a sample time is not supported when specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED.

please respond kindly

Answer 1

[Kiran Kintali]

HDL Coder natively supports integrating external HDL code into HDL Coder designs via its BlackBox architecture, available on both Subsystem and Model Reference blocks. To choose the BlackBox architecture:

1. Select the block you wish to use your own HDL code for
2. Right-click on it: choose HDL Code>HDL Block Properties
3. Change the Architecture to 'BlackBox'
4. Configure the block and its interface as desired

This is just a bare sketch of the process. Much more detail is available in the published documentation. Search for 'Black Box' and 'BlackBox' in the HDL Coder documentation for more detail.

Program Xilinx FPGAs Using HDL Coder with Xilinx System Generator for DSP

HDL Coder supports code generation for Simulink models constructed with a combination of blocks from Simulink and Xilinx-specific blocksets from System Generator for DSP. The System Generator Subsystem block in HDL Coder enables you to include models built with System Generator in Simulink as subsystems. HDL Coder uses System Generator to generate code from the subsystem blocks and integrates the complete design into synthesizeable HDL.

This approach enables you to:

• Use HDL Coder area and speed optimizations for Simulink components.
• Leverage Xilinx-optimized blocks in System Generator.
• Reuse legacy models built with Xilinx-specific blocks for simulation and code generation.

https://www.mathworks.com/content/dam/mathworks/tag-team/Objects/x/86457_92077_v01_Xilinx_WhitePaper.pdf

In summary, please consider using blackbox way of integrating RTL into HDLCoder or use combination of XSG and Simulink blocks as shown in the paper above.

[RAMACHANDRAREDDY KOTAPATI]

I am followed your pdf link while executing keep getting errors from fixed point conversion due to the warning getting from the unique input ports and also getting invalid design location but i keep same directory as design location.I use AND gate code for execution and do not have idea about the xilinx to matlab conversion code.so please help me .Thanks for your responding

[SUHANYA M S]

I'm getting the same error too. Just exploring black box feature with a simple AND gate written in VHDL. The file was synthesized with no errors. Imported the file with top level ports as A, B, C in the blackbox in Simulink. FPGA clock is set as 10ns. Simulink simulation time is also the same.

Attached the model file and error message. The config file was generated once the vhdl file (see below) was added to the blackbox. Please help.

[SUHANYA M S]

Imanaged to identify the error while compiling the slx file above. There were two semicolons after an if statement. Once they were removed, I did see the ouput.

The next problem arises when I try to generate the netlist using System Generator. I keep getting the same error. I've no idea how to get around this one. Unless I can generate a netlist, I can't try adding IP cores from Vivado! Please help.