Lane Detection on Simulink Programmable FPGA

Learn how to implement a pixel-stream based lane detection algorithm in Simulink, and deploy it to a Speedgoat Simulink-Programmable FPGA.
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Updated Thu, 29 Oct 2020 10:05:11 +0000
About
The Speedgoat Lane Detection on FPGA reference application demonstrates the implementation of a lane detection algorithm in Simulink using Vision HDL Toolbox and a Speedgoat Simulink-Programmable FPGA. For a detailed discussion of the workings of the algorithm, please refer to the original Vision HDL example. The differences to the original example include adaptions to work with 1080p image resolution (instead of 480p) and the HDMI interface of the Speedgoat IO333-325k-SFP FPGA module.
Learn How To
  • Use Vision HDL Toolbox™ to model a lane detection algorithm in Simulink®
  • Auto-generate VHDL code from your Simulink® model and deploy to Speedgoat Simulink Programmable FPGA I/O
  • Process high-resolution video streams with high sample frequency in real-time
  • Directly access video I/O such as HDMI with low latency
Getting Started
  1. Open MATLAB and open Simulink Project File
  2. Click in 'Getting Started' project shortcut
  3. Follow steps in the documentation
Watch Demo
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Cite As

Speedgoat Application Engineering Team (2024). Lane Detection on Simulink Programmable FPGA (https://github.com/Speedgoat-Application-Engineering-Team/Lane-Detection-on-FPGA/releases/tag/v1.1.0), GitHub. Retrieved .

MATLAB Release Compatibility
Created with R2019a
Compatible with R2019a
Platform Compatibility
Windows macOS Linux

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Version Published Release Notes
1.1.0

To view or report issues in this GitHub add-on, visit the GitHub Repository.
To view or report issues in this GitHub add-on, visit the GitHub Repository.