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Kiran Kintali


MathWorks

125 total contributions since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

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Answered
Delay balancing unsuccessful because Signal rate of value inf found.
Can you share the model and the version of MATLAB you are using that exhibits this behavior? Thanks.

7 days ago | 0

Answered
Delay balancing unsuccessful because Signal rate of value inf found.
Can you run HDL model advisor check shown below to see if you can detect the block? If the block with Inf sample time is not...

8 days ago | 0

Answered
How to convert a Simscape Electrical model into a Fixed-point HDL generable model ?
This workflow currently supports double, single and in future half precision formats. The workflow currently does not yet supp...

15 days ago | 1

| accepted

Answered
can a single model containing 2 different subsystems generate HDL and C code for the subsystems seperately?
Yes. You can generate code independently using embedded Coder and HDL Coder products for the two subsystems and integrate the co...

27 days ago | 1

Answered
HDL Coder to / downto order
This is a limitation due to an early decision made to emit vector of boolean to use 'TO' syntax and is not currently customizabl...

28 days ago | 0

| accepted

Answered
pir_core:pirudd:assertionFailed: Assertion failed: b:\matlab\src\cgir_hdl\dom_pir_core\cgtransformdriver.cpp:155:lsv_result != CG::transform::StructExplosion::RESULT_ERROR
This looks like an unexpected internal error. Can you contact techsupport@mathworks.com with reproduction steps? Thanks

2 months ago | 0

Answered
HDL Coder 'abs' : Double and complex data types not supported.
This is currently a limitation on the Abs block. https://www.mathworks.com/help/simulink/slref/mathfunction.html In the interi...

3 months ago | 0

Answered
Getting timing closure for HDL Coder IP with multicycle paths
Please contact support@mathworks.com for help on this topic. Can you share the Simulink model with us to better answer the quest...

3 months ago | 0

| accepted

Answered
Why do I receive an assertion in portmgr.cpp:340:Error: Invalid port index 13 requested when 12 is the max port index for comp
Thank you. Great to know you found a reasonable workaround for the issue. If you can still share the reproduction steps for the...

3 months ago | 0

Answered
Why do I receive an assertion in portmgr.cpp:340:Error: Invalid port index 13 requested when 12 is the max port index for comp
This is not expected and you are run into an internal error. Can you submit reproduction steps to support@mathworks.com? than...

3 months ago | 0

| accepted

Answered
how can i fixe problems status code 2
please send your code and reproduction steps to support@mathworks.com Thanks

3 months ago | 0

Answered
How to define parameter for HDL algorithm.
Can you please elaborate on your question? Have you looked at the product documentation? please reach out to support@mathworks....

4 months ago | 0

Answered
Simscape for HDL code generation
Support for multiple simscape networks is planned. Please share your usecases or sample models with us support@mathworks.com In...

4 months ago | 0

| accepted

Answered
Error during HDL Code generation: Not enough input arguments. Error in emlcprivate at 0
can you please contact support@mathworks.com with reproduction steps (design and test bench)? Thanks

4 months ago | 0

Answered
How to determine where HDL coder's clock-rate pipelining runs into an algebraic loop?
Please reach out to support@mathworks.com with reproduction steps. It looks like the highlight script that points to the problem...

4 months ago | 0

Answered
Connection problem between Zybo z7 10 and Matlab
The error seems to be from the “zynq” function, which originates from the Embedded Coder Zynq HSP (Hardware Support Package). We...

5 months ago | 0

Answered
How to write ladder logic in Simulink?
Hi John, Can you please check the capability to import and generate ladder diagrams in Simulink PLC Coder? Import Rockwell Aut...

8 months ago | 0

| accepted

Answered
Error in conversion of simulink model into verilog code?
Absence of the necessary files shows you seem to have installation issues. Can you please do a clean reinstall and if it doesn...

9 months ago | 0

| accepted

Answered
How to build a simulink model which can generate HDL coder to resize images or videos?
Sharing a HDL Coder friendly model to convert 720x1280 HDMI input signal to 240x320 video signal within Zynq PL side on ZC702, a...

9 months ago | 1

Answered
MATLAB CODE TO HDL
The file structure should be as follows 1) design under test file dut.m 2) test bench file dut_tb.m The file 'dut.m' ...

10 months ago | 0

Answered
HDL CODER. i need to deal with pins of the output port one by one not as 8 bit . how i can do this ?
HDLCoder does support specification of which pin of the 8 bit to use to map to the DUT. Following example demonstrates how to ...

10 months ago | 2

| accepted

Answered
Using direct lookup table as input to a matlab function block in simulink => error in "Check Block Compatibility" of "HDL Workflow Advisor"
Can you please send the reproduction steps to kiran.kintali@mathworks.com? We can help further analyze the issue. thanks

10 months ago | 0

Answered
HDL CODER. i need to deal with pins of the output port one by one not as 8 bit . how i can do this ?
Can you please check 'eml_hdl_design_patterns' for examples? It has bit twiddler blocks and ideas on how bitslice and stream d...

10 months ago | 0

Answered
How can I create a subsystem which performs the opposite of the Multiport Switch block?
function [y1, y2, y3] = fcn(u, sel) y1 = 0; y2 = 0; y3 = 0; switch sel case 1 y1 = u + 1; case 2 ...

11 months ago | 0

Answered
About hdlsllib/HDL RAMs blocks
hdl.RAM is a system object and all RAM system blocks can be configured within variations of the system object. They have identic...

11 months ago | 0

| accepted

Answered
need help to solve fxpopt with neural network algorithm problem
Hi, Can you tell us what kind of help you are looking for on this example? thanks

11 months ago | 0

Answered
errors due to simulation generation,black box unable for inherit sample time from system generator
HDL Coder natively supports integrating external HDL code into HDL Coder designs via its BlackBox architecture, available on bot...

12 months ago | 2

Answered
Simulink tutorials/ examples for Zynq
https://www.mathworks.com/hardware-support/zynq.html

12 months ago | 0

Answered
Using HDL coder for Matlab Function block of Simulink
kiran.kintali@mathworks.com Can you share sample abstract MATLAB code and testbench on what you are describing here? type "em...

12 months ago | 0

| accepted

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