Videos

Verify VHDL ® and Verilog ® using HDL simulators and FPGA-in-the-loop test benches with HDL Verifier™.
This interactive, two-day course provides a guided workflow to generate and optimize your HDL code. Attend a course today and learn to generate and verify HDL code from a Simulink model using HDL...
This session demonstrates how recent developments in MATLAB ® and Simulink ® reduce the cost of developing FPGA and ASIC applications, through strong integration with...
Use HDL Verifier to import handwritten or legacy VHDL or Verilog for cosimulation with Simulink.
Allegro Microsystems explains how they are leveraging MATLAB and Simulink for rapid prototyping, streamlined UVM-based verification, and automatic RTL code generation for mixed signal sensor ICs.
This presentation focuses on integrating checks based on MATLAB® into SV/UVM-based digital verification environments using DPI-C flow.
Engineers complete communication payload design simulation and hardware validation and verification with Simulink.
Perform FPGA-based verification with custom boards using MATLAB ® and Simulink ® as test benches. Figures based on or adapted from figures and text owned by Xilinx,...
This presentation focuses on integrating checks based on MATLAB® into SV/UVM-based digital verification environments using DPI-C flow.
Generate a SystemVerilog DPI-C reference model for use in UVM simulation from MATLAB ® using HDL Verifier™.
HDL Verifier exports MATLAB functions to help speed UVM test environment creation for simulation in Synopsys VCS and Verdi.
Insert test points into SystemVerilog DPI components generated by HDL Verifier™.
Perform FPGA-based verification with custom boards using MATLAB ® and Simulink ® as test benches. Figures based on or adapted from figures and text owned by Xilinx,...
Utilize the HDL Verifier™ FPGA-in-the-loop capability with PCI Express® for designs on an Intel® Cyclone® V GT FPGA development kit.
Utilize the HDL Verifier™ FPGA-in-the-loop capability with PCI Express® for designs on a Xilinx® Kintex® KC705 evaluation kit.
Analyze internal signals to a free-running FPGA directly in MATLAB or Simulink.
MATLAB as AXI Master in HDL Verifier provides read/write access to on-board memory locations on Intel® FPGA and SoC boards from a MATLAB session. See how it’s used to control an IP core generated by HDL Coder™ on an Intel MAX® 10 FPGA.
MATLAB as AXI Master in HDL Verifier provides read/write access to on-board memory locations on Xilinx FPGA and Zynq SoC boards from a MATLAB session. See how it’s used to control an IP core generated by HDL Coder on an Xilinx Kintex-7 FPGA.