Getting Started with HDL Code Generation
These resources provide a path to help engineers ramp up on generating HDL Code from Simulink® blocks, MATLAB® code, and Stateflow® charts. The program features a variety of resources including videos, self-paced training, webinars, and on-site sessions.
Learn the essentials of MATLAB through this free, two-hour introductory tutorial on commonly used features and workflows.
Online training
Learn the basics of how to create, edit, and simulate models in Simulink with this free, three-hour introductory tutorial.
Online training
Explore how you can use Simulink to design, simulate, implement, and test a variety of time-varying systems.
Recorded webinar
This three-day course provides a comprehensive introduction to the MATLAB technical computing environment.
Online and instructor-led training
This two-day course is for engineers who are new to system and algorithm modeling and design validation in Simulink.
Instructor-led training
Learn about Model-Based Design and how to use Simulink to create block diagrams and simple models.
Documentation
Watch this five-part video guide to learn about FPGA design with MATLAB. Discover the key factors to consider when targeting a signal-processing algorithm to FPGA or ASIC hardware.
Video demonstration
Use the strengths of MATLAB and Simulink to deploy an algorithm to hardware.
Video demonstration
Learn how to take signal processing and communications designs from floating point to efficient fixed-point implementation on FPGAs.
Recorded webinar
Generate target-independent synthesizable VHDL or Verilog code directly from single-precision floating-point models.
Video demonstration
Learn how to connect FPGA and ASIC implementation and verification to system-level design in Simulink using HDL Coder™ and HDL Verifier™.
Recorded webinar
This tutorial will guide you through the steps necessary to implement a MATLAB algorithm in FPGA hardware.
Document and examples
These guidelines will help you adopt HDL Coder for your design and include examples to illustrate selected concepts.
Document and examples
This three-day course will review DSP fundamentals from the perspective of implementation within the FPGA fabric.
Instructor-led training
This two-day course shows how to generate and verify HDL code from a Simulink model using HDL Coder and HDL Verifier.
Instructor-led training
Generate SystemVerilog DPI components to speed verification environment creation, debug issues with cosimulation between MATLAB or Simulink and HDL simulation, and learn how to eliminate bugs much earlier through broader collaboration.
Recorded webinar
Generate a SystemVerilog DPI-C reference model for use in UVM simulation from MATLAB using HDL Verifier.
Video demonstration
Use HDL Verifier to import handwritten or legacy VHDL or Verilog for cosimulation with Simulink.
Video demonstration
Perform FPGA-based verification with custom boards using MATLAB and Simulink as test benches.
Video demonstration
Analyze internal signals to a free-running FPGA directly in MATLAB or Simulink.
Video demonstration
MATLAB as AXI Master in HDL Verifier provides read/write access to on-board memory locations on Xilinx® FPGA and Zynq® SoC boards from a MATLAB session. See how it’s used to control an IP core generated by HDL Coder on an Xilinx Kintex®-7 FPGA.
Video demonstration
MATLAB as AXI Master in HDL Verifier provides read/write access to on-board memory locations on Intel® FPGA and SoC boards from a MATLAB session. See how it’s used to control an IP core generated by HDL Coder on an Intel MAX® 10 FPGA.
Video demonstration
Use MATLAB and Simulink to program Intel SoC FPGAs in a prototyping workflow.
Video demonstration
Learn how you can use MATLAB and Simulink to model, simulate, test, and deploy communications algorithms on Zynq and AD9361-based production platforms.
Recorded webinar
Capture, measure, and characterize RF performance in millimeter-wave bands using MATLAB and Simulink and the Avnet mmWave Radio Development Kit with Xilinx Zynq UltraScale+ RFSoC Gen-3
Video demonstration
Learn the considerations, workflow, and techniques for targeting a vision processing algorithm to FPGA hardware.
Video series
The goal of the webinar is to provide an overview of the real-time simulation and testing (RTST) solution from MathWorks and Speedgoat for RCP/HIL. Take your control design from a desktop simulation and test it in real time with hardware and I/O.
Recorded webinar
Watch this video of a hardware-in-the-loop (HIL) simulation of a motor and inverter running on an FPGA at a time-step of 1 µs.
Recorded webinar
This hands-on, two-day course focuses on developing and configuring models in Simulink and deploying on Xilinx Zynq-7000 All Programmable SoCs.
Instructor-led training
This hands-on, one-day course focuses on modeling designs based on software-defined radio in MATLAB and Simulink and configuring and deploying on the ADI RF SOM.
Instructor-led training
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