Jack Erickson, MathWorks
Learn how to improve verification productivity by re-using MATLAB algorithms and Simulink models with HDL Verifier.
The largest amount of effort in an ASIC or FPGA design project is typically functional verification. Connecting MATLAB or Simulink to the verification process enables re-use of system- and algorithm-level designs and tests for speeding creation of RTL verification environments, including the Universal Verification Methodology (UVM).
Learn the latest techniques available, including:
About the Presenter
Jack Erickson is responsible for product marketing and product management for the HDL product family at MathWorks. Prior to joining MathWorks, he spent over 20 years at Cadence Design Systems, Inc., as an applications engineer and then in product marketing for simulation, RTL synthesis, and high-level synthesis. He has a BSEE from Tufts University and an MBA from Worcester Polytechnic Institute.
Recorded: 26 May 2016