Prototype and Deploy Deep Learning Networks on FPGAs and SoCs

Overview

For system designers looking to integrate deep learning into their FPGA-based applications, the talk helps teach the challenges and considerations for deploying to FPGA hardware and details the workflow in MATLAB. We will briefly show how to explore and prototype trained networks on FPGAs using prebuilt bitstreams from MATLAB. You can further customize your network to meet your performance requirements and hardware resource usage, generate HDL, and integrate it into an FPGA-based edge inference system.

Highlights

• Prototype network without FPGA programming using available bitstreams for popular FPGA development boards
• Profile networks and use quantization to improve performance
• Configure and Generate Custom Deep Learning Processor
• Deploy custom RTL implementations of the deep learning processor to any FPGA, ASIC, or SoC device

About the Presenter

Vidya Viswanathan is a Senior Application Engineer at MathWorks India specializing in design and implementation of digital signal processing applications. She works closely with customers across domains to help them adopt MATLAB® and Simulink®. Her areas of interest include FPGA and ASIC design, wireless communication, and image processing. Vidya holds a bachelor's degree in electronics and communication engineering from M. S. Ramaiah Institute of Technology and a master's degree in communication and signal processing from Indian Institute of Technology Hyderabad.