dlhdl.ProcessorConfig Class

R2026b

Namespace: dlhdl

Configure custom deep learning processor

Description

Use the dlhdl.ProcessorConfig class to configure a custom processor. Use the dlhdl.buildProcessor function to generate a custom deep learning processor IP core from a dlhdl.ProcessorConfig object.

Creation

dlhdl.ProcessorConfig(Name=Value) creates a custom processor configuration object, with the options specified by one or more name-value arguments.

Properties

System-Level Properties

ReferenceDesign — Reference design template for system integration

"AXI-Stream DDR Memory Access : 3-AXIM" (default) | "Deep Learning with Preprocessing Interface" | "AXI-Stream BRAM Memory Access : 3-AXIM"

Reference design template for system integration, specified as one of these values:

• "AXI-Stream DDR Memory Access : 3-AXIM"

• "Deep Learning with Preprocessing Interface"

• "AXI-Stream BRAM Memory Access : 3-AXIM"

The dlhdl.buildProcessor function ignores this property if TargetPlatform is "Generic Deep Learning Processor".

SynthesisTool — Synthesis tool for bitstream generation

"Xilinx Vivado" (default) | "Altera Quartus II" | "Xilinx ISE"

Synthesis tool for bitstream generation, specified as one of these values:

• "Xilinx Vivado"

• "Altera Quartus II"

• "Xilinx ISE"

SynthesisToolChipFamily — FPGA chip family name

"Zynq UltraScale+" (default) | "Artix7" | "Kintex7" | "Kintex UltraScale+" | "Spartan7" | "Virtex7" | "Virtex UltraScale+" | "Zynq" | "Arria 10" | "Arria V GZ" | "Cyclone 10 GX" | "Stratix 10" | "Stratix V"

FPGA chip family name, specified as one of these values:

• "Zynq UltraScale+"

• "Artix7"

• "Kintex7"

• "Kintex UltraScale+"

• "Spartan7"

• "Virtex7"

• "Virtex UltraScale+"

• "Zynq"

• "Arria 10"

• "Arria V GZ"

• "Cyclone 10 GX"

• "Stratix 10"

• "Stratix V"

SynthesisToolDeviceName — FPGA device part number

"" (default)

FPGA device part number, specified as a character vector or string scalar. When you specify the TargetPlatform, Deep Learning HDL Toolbox™ populates this property with the default value for that target platform.

SynthesisToolPackageName — Synthesis tool part number

"" (default)

Synthesis tool part number, specified as a character vector or string scalar. When you specify the TargetPlatform property, Deep Learning HDL Toolbox populates this property with the default value for that target platform.

SynthesisToolSpeedValue — FPGA speed grade

"" (default)

FPGA speed grade, specified as a character vector or string scalar. When you specify the TargetPlatform property, Deep Learning HDL Toolbox populates this property with the default value for that target platform.

Example: "-2"

TargetFrequency — Target clock frequency for FPGA design

200 (default) | positive integer

Target clock frequency for FPGA design, specified as a positive integer in MHz.

Example: 220

TargetPlatform — FPGA target platform for deployment

"Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit" (default) | "Generic Deep Learning Processor" | "Intel Arria 10 SoC development kit" | "Xilinx Zynq ZC706 evaluation kit" | "Xilinx Kintex-Ultrascale KCU105 evaluation board"

FPGA target platform for deployment, specified as one of these values:

• "Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit"

• "Generic Deep Learning Processor"

• "Intel Arria 10 SoC development kit"

• "Xilinx Zynq ZC706 evaluation kit"

• "Xilinx Kintex-Ultrascale KCU105 evaluation board"

Bitstream — Bitstream name

"arria10soc_single" | "arria10soc_int8" | "arria10soc_lstm_single" | "zc706_single" | "zc706_int8" | "zcu102_single" | "zcu102_int8" | "zcu102_lstm_single" | "zc706_lstm_single"

Bitstream name, specified as one of these values:

• "arria10soc_single"

• "arria10soc_int8"

• "arria10soc_lstm_single"

• "zc706_single"

• "zc706_int8"

• "zcu102_single"

• "zcu102_int8"

• "zcu102_lstm_single"

• "zc706_lstm_single"

RAMDirective — RAM mapping directive for synthesis

"block" (default)

RAM mapping directive for synthesis, specified as a character vector or string scalar. This property controls which physical RAM type the synthesis tool targets when mapping parameters from the deep learning processor IP core. Code generation supports the Quartus and Xilinx synthesis tools. This table shows the supported RAMDirective values for each tool.

Synthesis Tool	RAMDirective Values
Quartus®	"logic" "M9K" "M10K" "M20K" "M144K" "MLAB"
Xilinx®	"block" "distributed" "registers" "ultra"

If you set this property to a value other than "block" and use the estimateResources method on the dlhdl.ProcessorConfig object, the method displays a warning that explains that it cannot estimate the RAM usage because it bases its resource estimations only on block RAM usage. If you set the TargetPlatform property to "Generic Deep Learning Processor", the default value for RAMDirective is "".

The Deep Learning HDL Toolbox validates the property value against the SynthesisTool property value. If you change the SynthesisTool property after setting the RAMDirective property, you must verify that the RAMDirective property value is valid for the new synthesis tool.

Data Types: char | string

Top-Level Properties

RunTimeControl — Interface type for runtime control signals

"register" (default) | "port"

Interface type for runtime control signals, specified as "register" or "port".

RunTimeStatus — Interface type for runtime status signals

"register" (default) | "port"

Interface type for runtime status signals, specified as "register" or "port".

InputStreamControl — Interface type for input stream control

"register" (default) | "port"

Interface type for input stream control, specified as "register" or "port".

OutputStreamControl — Interface type for output stream control

"register" (default) | "port"

Interface type for output stream control, specified as "register" or "port".

SetupControl — Interface type for setup control signals

"register" (default) | "port"

Interface type for setup control signals, specified as "register" or "port".

ProcessorDataType — Data type for processor computations

"single" (default) | "int8"

Data type for processor computations, specified as "single" or "int8".

UseVendorLibrary — Enable vendor-specific IP libraries for HDL code generation

"on" (default) | "off"

Enable vendor-specific IP libraries for HDL code generation, specified as a character vector or string scalar. When you set the option to "on", Deep Learning HDL Toolbox uses a mixture of native floating-point (NFP) and vendor-specific floating-point IPs to generate HDL code. When you set the option to "off", Deep Learning HDL Toolbox uses NFP libraries to generate HDL code.

When you set ProcessorDataType to "int8", you must set UseVendorLibrary to "off". When ProcessorDataType is "single", MATLAB automatically sets this option to "on".

Example: UseVendorLibrary = "on"

LayerNormalizationBlock — Option to enable layer normalization hardware block generation

"off" (default) | "on"

Option to enable layer normalization hardware block generation, specified as "on" or "off". When you enable this layer, Deep Learning HDL Toolbox enables generation of the fc and custom processing modules. To enable this option you must set ProcessorDataType to "single".

Example: LayerNormalizationBlock = "on"

Convolution Module Properties

ModuleGeneration — Option to enable convolution module generation

"on" (default) | "off"

Option to enable convolution module generation, specified as "on" or "off".

LRNBlockGeneration — Option to enable local response normalization (LRN) block generation in the convolution module

"off" (default) | "on"

Option to enable local response normalization (LRN) block generation in the convolution module, specified as "on" or "off".

SegmentationBlockGeneration — Option to enable segmentation block generation in the convolution module

"on" (default) | "off"

Option to enable segmentation block generation in the convolution module, specified as "on" or "off".

GELUBlockGeneration — Option to enable GELU activation block generation in the convolution module

"off" (default) | "on"

Option to enable GELU activation block generation in the convolution module, specified as "on" or "off".

ConvThreadNumber — Number of parallel convolution threads

16 (default) | 4 | 9 | 16 | 25 | 36 | 64 | 81 | 100 | 121 | 144 | 169 | 196 | 225 | 256 | positive integer

Number of parallel convolution threads, specified as one of these values:

• 4

• 9

• 16

• 25

• 36

• 64

• 81

• 100

• 121

• 144

• 169

• 196

• 225

• 256

To set ConvThreadNumber to 81, 100, 121, 144, 169, 196, 225, or 256, you must set the ProcessorDataType property to "int8".

InputMemorySize — Input memory size for the convolution module

[227 227 3] (default) | three-element vector

Input memory size for the convolution module, specified as a three-element vector.

OutputMemorySize — Output memory size for the convolution module

[227 227 3] (default) | three-element vector

Output memory size for the convolution module, specified as a three-element vector.

FeatureSizeLimit — Maximum feature map size for the convolution module

2048 (default) | positive integer

Maximum feature map size for the convolution module, specified as a positive integer.

Fully Connected Module Properties

ModuleGeneration — Option to enable fully connected module generation

"on" (default) | "off"

Option to enable fully connected module generation, specified as "on" or "off".

SoftmaxBlockGeneration — Option to enable softmax block generation in the fully connected module

"off" (default) | "on"

Option to enable softmax block generation in the fully connected module, specified as "on" or "off". When you set this property to "off", Deep Learning HDL Toolbox implements the Softmax layer in software.

GELUBlockGeneration — Option to enable GELU activation block generation in the fully connected module

"off" (default) | "on"

Option to enable GELU activation block generation in the fully connected module, specified as "on" or "off".

FCThreadNumber — Number of parallel fully connected threads

4 (default) | 2 | 4 | 8 | 16 | 32 | 64 | positive integer

Number of parallel fully connected threads, specified as one of these values:

• 2

• 4

• 8

• 16

• 32

• 64

To set FCThreadNumber to 32 or 64, you must set the ProcessorDataType property to "int8".

InputMemorySize — Input memory size for the fully connected module

25088 (default) | positive integer

Input memory size for the fully connected module, specified as a positive integer.

OutputMemorySize — Output memory size for the fully connected module

4096 (default) | positive integer

Output memory size for the fully connected module, specified as a positive integer.

Custom Module Properties

ModuleGeneration — Option to enable custom module generation

"on" (default) | "off"

Option to enable custom module generation, specified as "on" or "off".

Addition — Option to enable addition layer generation in the custom module

"on" (default) | "off"

Option to enable addition layer generation in the custom module, specified as "on" or "off".

MishLayer — Option to generate mish activation layer in the custom module

"off" (default) | "on"

Option to generate mish activation layer in the custom module, specified as "on" or "off".

Multiplication — Option to enable multiplication layer generation in the custom module

"on" (default) | "off"

Option to enable multiplication layer generation in the custom module, specified as "on" or "off".

Resize2D — Option to enable resize2D layer generation in the custom module

"off" (default) | "on"

Option to enable resize2D layer generation in the custom module, specified as "on" or "off".

Sigmoid — Option to enable sigmoid layer generation in the custom module

"off" (default) | "on"

Option to enable sigmoid layer generation in the custom module, specified as "on" or "off".

SwishLayer — Option to enable swish activation layer generation in the custom module

"off" (default) | "on"

Option to enable swish activation layer generation in the custom module, specified as "on" or "off".

TanhLayer — Option to enable tanh activation layer generation in the custom module

"off" (default) | "on"

Option to enable tanh activation layer generation in the custom module, specified as "on" or "off".

InputMemorySize — Input memory size for custom module

40 (default) | positive integer

Input memory size for the custom module, specified as a positive integer.

OutputMemorySize — Output memory size for custom module

120 (default) | positive integer

Output memory size for the custom module, specified as a positive integer.

Methods

Public Methods

buildCalibrationBitstream	Generate calibration bitstream to obtain double data rate (DDR) RAM response time
deployCalibrationBitstream	Deploy calibration bitstream and generate calibration data file
getModuleProperty	Use the getModuleProperty method to get values of module properties within the dlhdl.ProcessorConfig object
setModuleProperty	Use the setModuleProperty method to set properties of modules within the dlhdl.ProcessorConfig object
estimatePerformance	Retrieve layer-level latencies and performance by using estimatePerformance method
estimateResources	Return estimated resources used by custom bitstream configuration
optimizeConfigurationForNetwork	Update network-specific deep learning processor configuration with optimized deep learning processor configuration
openCustomLayerModel	Open a generated custom layer verification model to verify your custom layers
registerCustomLayer	Register the custom layer definition and Simulink model representation of the custom layer
verifyCustomLayerModel	Verify the functionality and accuracy of the custom layer by using the generated custom layer verification model

Examples

Create a Custom Processor Configuration

Create a dlhdl.ProcessorConfig object.

hPC = dlhdl.ProcessorConfig

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                         GELUBlockGeneration: 'off'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'
                            UseVendorLibrary: 'on'
                     LayerNormalizationBlock: 'off'
                                RAMDirective: 'block'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 200
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Modify Properties of a Processor Configuration

Modify the TargetPlatform, SynthesisTool, and TargetFrequency properties of a dlhdl.ProcessorConfig object.

hPC = dlhdl.ProcessorConfig;
hPC.TargetPlatform = 'Xilinx Zynq ZC706 evaluation kit';
hPC.SynthesisTool = 'Xilinx Vivado';
hPC.TargetFrequency = 180;
hPC

The result is:

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                         GELUBlockGeneration: 'off'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'
                            UseVendorLibrary: 'on'
                     LayerNormalizationBlock: 'off'
                                RAMDirective: 'block'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq ZC706 evaluation kit'
                             TargetFrequency: 180
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq'
                     SynthesisToolDeviceName: 'xc7z045'
                    SynthesisToolPackageName: 'ffg900'
                     SynthesisToolSpeedValue: '-2'

Retrieve ProcessorConfig Object for a Bitstream

Retrieve the ProcessorConfig object for the zcu102_single bitstream.

hPC = dlhdl.ProcessorConfig(Bitstream = "zcu102_single")

The result is:

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                         GELUBlockGeneration: 'off'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'on'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'
                            UseVendorLibrary: 'on'
                     LayerNormalizationBlock: 'off'
                                RAMDirective: 'block'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 220
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Set the Module Data Type to int8

Create a custom processor configuration.

hPC = dlhdl.ProcessorConfig;

Set the ProcessorDataType property to int8. When you set the ProcessorDataType property to int8, you must set the UseVendorLibrary property to "off".

hPC.ProcessorDataType = 'int8'
hPC.UseVendorLibrary = 'off'

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                         GELUBlockGeneration: 'off'
                            ConvThreadNumber: 16
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                         GELUBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                     Sigmoid: 'off'
                                  SwishLayer: 'off'
                                   TanhLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'int8'
                            UseVendorLibrary: 'off'
                     LayerNormalizationBlock: 'off'
                                RAMDirective: 'block'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 200
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Version History

Introduced in R2020b

R2026b: Specify the RAM mapping strategy for deep learning processors

You can now specify the RAM mapping strategy for deep learning processor IP cores by using the RAMDirective property. Use this property to direct the synthesis tool to map internal deep learning processor memories to a specific physical RAM type.

R2026a: Support for larger convolution thread numbers

You can now set the ConvThreadNumber to 81, 100, 121, 144, 169, 196, 225, or 256, when you set the ProcessorDataType property to int8.

R2026a: Support for smaller fully connected thread numbers

You can now set the FCThreadNumber property to 2.