Altera FPGA and SoC Devices
R2026bHDL Coder™ Support Package for Intel® FPGA and SoC Devices enables you to generate HDL IP cores from MATLAB® and Simulink® designs and integrate them into Altera FPGA designs using Altera Quartus® Prime Platform Designer. You can generate synthesizable HDL code, package it as an IP core, and deploy it to supported Altera FPGA and SoC devices. When used together with Embedded Coder®, the support package enables a hardware–software co‑design workflow for Intel SoC devices. This workflow combines HDL and C code generation and supports simulation, prototyping, verification, and implementation. For more information, see Hardware-Software Co-Design Workflow for SoC Platforms.
The support package includes board definition files for supported Intel FPGA and SoC boards and supports FPGA‑in‑the‑Loop (FIL) simulation. With FIL simulation, you can verify existing HDL designs by running them on real hardware directly from MATLAB or Simulink. FPGA Data Capture support lets you observe internal signals while the design is running on the FPGA or SoC device. Using AXI Manager, you can read from and write to on‑board memory locations from MATLAB or Simulink.
Using the HDL Coder Support Package for Intel FPGA and SoC Devices, you can model, simulate, analyze, and prototype complete hardware and software architectures on Intel SoC platforms. Key capabilities include I/O data recording, software profiling, FPGA diagnostics, Linux® customization, software and hardware code generation (with the required code generation products), and custom board support.
The support package also provides prebuilt FPGA bitstreams for prototyping deep learning and vision networks, such as Series Networks and YOLO, on supported Altera FPGA and SoC boards. To deploy your design to the Altera FPGA and SoC device, you must install the HDL Coder Support Package for Intel FPGA and SoC Devices. For installation information, see HDL Coder Supported Hardware.
| Device Family | Board | Available Reference Designs |
|
Arria® 10 SoC |
Altera Arria 10 SoC development kit | |
|
Cyclone® V |
Cyclone V SoC development kit - Rev.C | |
|
Cyclone V SoC development kit - Rev.D | ||
|
Arrow SoCKit development board | ||
|
Arria 10 |
Arria 10 GX FPGA development kit | PCIe AXI Manager with External DDR4 Memory Access JTAG AXI Manager with External DDR4 Memory Access |
|
Altera MAX® 10 |
Arrow® DECA MAX 10 FPGA evaluation kit |
Note
To extend support to new hardware, see Deploy IP Core on Custom Hardware.
Categories
- Setup and Configuration
Download and install support package for use with third-party EDA tools and supported hardware
- Get Started With Hardware-Software Co-Design
Deploy generated HDL code on a target hardware platform
- Generate an IP Core and Bitstream
Generate HDL IP core and bitstream that contain HDL code for deployment on standalone Altera FPGA boards and SoC Devices
- FPGA Verification and Debug
Debug and test HDL code on Intel FPGAs
- SoC Modeling and Generation
Design, analyze, and prototype for Intel SoC and FPGA devices
- Embedded Targets
Generate code for the ARM® Cortex®-A cores on Altera SoC FPGA Devices
- Deep Learning
Prototype different network architectures on supported Altera FPGAs and SoCs
Featured Examples
Get Started with IP Core Generation for Intel SoC Devices
Use the Simulink Toolstrip and Simulink Interface along with the hardware-software co-design workflow to blink LEDs at various frequencies on the Arrow® SoCKit® evaluation kit.
Get Started with IP Core Generation for Intel Quartus Pro Based Devices
Build a reference design by using Intel® Platform Designer® and then deploy the design to an Intel® Arria 10 SoC. A reference design defines the SoC architecture, including components and their connections. When you create a reference design, HDL Coder generates an IP core that uses the reference design to program the SoC board.
