Check for presence of reals in generated HDL code

Specify whether to check for reals in the generated HDL code

Model Configuration Pane: Global Settings / Advanced

Description

Specify whether to check for reals in the generated HDL code.

Settings

Error | None | Warning

Default: Error

None

Do not check for reals in the generated HDL code.

Warning

Checks and warns of presence of real data types in the generated HDL code. Real data types in the generated HDL code are not synthesizable on target FPGA devices.

Error

Checks and generates an error if the generated HDL code uses real data types. If you are generating code for simulation purposes and not for synthesizing your design, you can change this setting to Warning or None. To generate synthesizable HDL code, select the model configuration parameter Use Floating Point.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','TreatRealsInGeneratedCodeAs','Warning')
makehdl('sfir_fixed/symmetric_fir')

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','TreatRealsInGeneratedCodeAs','Warning')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: TreatRealsInGeneratedCodeAs
Type: character vector
Value: 'None' | 'Warning' | 'Error'
Default: 'Error'

Version History

Introduced in R2017b

See Also

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