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Dual Rate Dual Port RAM

Dual Port RAM that supports two rates

  • Library:
  • HDL Coder / HDL RAMs

  • Dual Rate Dual Port RAM block

Description

The Dual Rate Dual Port RAM block models a RAM that supports simultaneous read and write operations to different addresses at two clock rates. Port A of the RAM can run at one rate, and port B can run at a different rate.

In high-performance hardware applications, you can use this block to access the RAM twice per clock cycle. If you generate HDL code, this block maps to a dual-clock dual-port RAM in most FPGAs.

Simultaneous Access

You can access different addresses from ports A and B simultaneously. You can also read the same address from ports A and B simultaneously.

However, do not access an address from one RAM port while it is being written from the other RAM port. During simulation, if you access an address from one RAM port at the same time as you write that address from the other RAM port, the software reports an error.

Read-During-Write Behavior

The RAM has write-first behavior. When you write to the RAM, the new write data is immediately available at the output port.

Ports

Input

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Data that you write into the RAM memory location when we_A is true. The data inherits the width and data type from the input signal. din_A can be a double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data type: scalar fixed point, integer, or complex

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Address that you write the data into when we_A is true. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data Types: uint8 | uint16 | uint32 | uint64 | fixed point

Write enable for RAM port A. Set we_A to true for a write operation, or false for a read operation.

Data Types: Boolean

Data that you write into the RAM memory location when we_B is true. The data inherits the width and data type from the input signal. din_B can be a double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data type: scalar fixed point, integer, or complex

Data Types: int8 | int16 | int32 | int64 | fixed point

Address that you write the data into when we_B is true. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data type: scalar fixed point, integer, or complex

Data Types: int8 | int16 | int32 | int64 | fixed point

Write enable for RAM port B. Set we_B to true for a write operation, or false for a read operation.

Data Types: Boolean

Output

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Output data from RAM port A address, addr_A.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Output data from RAM port B address, addr_B.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Parameters

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Minimum bit width is 2, and maximum bit width is 28.

Programmatic Use

Block parameter: ram_size
Type: string scalar | character vector
Value: A minimum value of 2 and maximum value of 28
Default: '8'

Algorithms

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HDL code generated for RAM blocks has:

  • A latency of one clock cycle for read data output.

  • No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.

Code generation for a RAM block creates a separate file, blockname.ext. blockname is derived from the name of the RAM block. ext is the target language file name extension.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2014a