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fpga

R2026b

Data transfer object to enable data read and write operations from MATLAB to target FPGA or SoC device

Description

This object represents a connection from MATLAB® to the target FPGA or SoC device. To interact with the target device, use this object with the functions listed in Object Functions.

Creation

Description

hFPGA = fpga(Vendor) creates a hardware object that you can use to connect to your target Intel® or Xilinx® pure-FPGA device.

example

hFPGA= fpga(p) creates a hardware object by taking in a processor connection object intelsoc or xilinxsoc that you can use to connect to your target Intel or Xilinx SoC device.

example

hFPGA= fpga(jtagObj) creates a hardware object by taking in a JTAG connection object jtagchain that you can use to access registers and AXI memory on your target Intel or Xilinx FPGA or SoC device over a JTAG interface.

example

Input Arguments

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Connect to an Intel or Xilinx pure-FPGA target device from MATLAB.

When connecting to an SoC board, specify a processor connection object as the input.

Example: hFPGA = fpga("Intel")

Data Types: string | char

For SoC boards, specify a processor connection object as the input when creating the FPGA connection object. Pass in a xilinxsoc object for Xilinx SoC board. Pass in an intelsoc object for an Intel SoC board.

Example: hFPGA = fpga(p)

For FPGA or SoC boards, specify a JTAG connection object as the input when creating the FPGA connection object. Pass in a jtagchain object to identify the target Xilinx or Intel FPGA or SoC device and establish a JTAG connection for AXI memory access.

Example: hFPGA = fpga(jtagObj)

Output Arguments

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Connection from MATLAB to the FPGA on the Xilinx or Intel board. You can use this connection to interact with the hardware board and attached devices.​

Object Functions

Use the object functions to interact with your FPGA or SoC device.

addRegisterInterfaceWrite data to IP core or read data from IP core using AXI4 or AXI4-Lite interface
addAXI4StreamInterfaceWrite data to IP core or read data from IP core using AXI4-Stream interface
addMemoryInterfaceAccess memory regions on your FPGA or SoC hardware
mapPortMaps a DUT port to specified AXI4 interface in HDL IP core
readMemoryRead data from memory regions on FPGA or SoC hardware
writeMemoryWrite data to memory regions on FPGA or SoC hardware
writePortWrite data to a DUT port from MATLAB
readPortReads output data and returns it with the port data type and dimension
releaseRelease the hardware resources associated with the fpga object

Examples

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Create an fpga object to connect to a Xilinx target device.

Create an fpga object with Vendor as Xilinx.

hFPGA = fpga("Xilinx")
hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Create an fpga object to connect to an Intel target.

Create an fpga object with Intel as Vendor.

hFPGA = fpga("Intel")
hFPGA = 

  fpga with properties:

       Vendor: "Intel"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Create a hardware processor object to connect to a Xilinx SoC board. You can use the object to program your FPGA on-board the SoC board at the MATLAB command-line and to create an fpga object that connects to the FPGA through the processor on the SoC board.

Create a Xilinx processor hardware object and connect to the processor on-board the Xilinx SoC board.​

p = xilinxsoc('192.168.1.101', 'root', 'root');

Program the FPGA and set the corresponding device tree from processor on the SoC board by using the xilinxsoc object function programFPGA.

programFPGA(p, "myBitstream.bit", "myDeviceTree.dtb");

For more information on device trees, see Generate Device Tree for IP Core.

Connect to the FPGA on-board the SoC board by using the fpga function. Use the processor hardware object p as an input to the fpga function.

f = fpga(p);

Use a jtagchain object with the fpga object to access DUT ports mapped to AXI4-Lite registers over a JTAG interface.

Create a JTAG connection object for the target FPGA vendor. The jtagchain object detects the devices in the JTAG scan chain and stores the JTAG connection information.

jtagObj = jtagchain("AMD");

Create an FPGA hardware object by using the JTAG connection object. Use the FPGA hardware object to access AXI registers and memory on the target FPGA through the JTAG interface.

hFPGA = fpga(jtagObj);

Add an AXI4-Lite register interface to the FPGA hardware object by using the addRegisterInterface function.

addRegisterInterface(hFPGA, ...
    "InterfaceID","AXI4-Lite", ...
    "BaseAddress",0xA0000000, ...
    "AddressRange",0x10000, ...
    "DriverAddressMode","Full");

Create an input DUT port object and map it to the AXI4-Lite register interface.

hPortIn = hdlcoder.DUTPort("h_in1", ...
    "Direction","IN", ...
    "DataType",numerictype(1,16,10), ...
    "Dimension",[1 1], ...
    "IOInterface","AXI4-Lite", ...
    "IOInterfaceMapping","0x100");

mapPort(hFPGA,hPortIn);

Write data to the mapped DUT port by using the writePort function.

writePort(hFPGA,"h_in1",5);

Create an output DUT port object and map it to the AXI4-Lite register interface.

hPortOut = hdlcoder.DUTPort("h_out1", ...
    "Direction","OUT", ...
    "DataType",numerictype(1,16,10), ...
    "Dimension",[1 1], ...
    "IOInterface","AXI4-Lite", ...
    "IOInterfaceMapping","0x104");

mapPort(hFPGA,hPortOut);

Read data from the mapped DUT port by using the readPort function.

data = readPort(hFPGA,"h_out1")

Version History

Introduced in R2020b