Target Frequency

R2026b

Clock frequency for generated HDL design

Model Configuration Pane: Target

Description

This configuration parameter is in the Objectives Settings section of the HDL Code Generation > Target pane of the Configuration Parameters dialog box. By using this parameter, you can specify the target frequency in MHz for multiple features and workflows. To set the target frequency, first specify the Synthesis Tool.

Settings

0 (Default)

This setting is the target frequency in MHz for multiple features and workflows that HDL Coder™ supports. The supported features are:

FPGA floating-point target library mapping: Specify the target frequency that you want the IP to achieve when you use ALTERA MEGAFUNCTION (ALTERA FP FUNCTIONS). If you do not specify the target frequency, HDL Coder sets the target frequency to a default value of 200 MHz. See also Generate HDL Code for Vendor-Specific FPGA Floating-Point Target Libraries.
Adaptive pipelining: If your design uses multipliers, specify the synthesis tool and the target frequency. Based on these settings, HDL Coder estimates the number of pipelines that can be inserted to improve area and timing on the target platform. If you do not specify the target frequency, HDL Coder uses a target frequency of 0 MHz and does not insert adaptive pipelines. See also Specify Adaptive Pipelining Settings.

You can also set the target frequency by using the Target Frequency (MHz) setting in the Set Target Frequency task in the HDL Workflow Advisor.

Specify the target frequency for these workflows:

Generic ASIC/FPGA: To specify the target frequency that you want your design to achieve. HDL Coder generates a timing constraint file for that clock frequency. It adds the constraint to the FPGA synthesis tool project that you create in the Create Project task. If the target frequency is not achievable, the synthesis tool generates an error.
IP Core Generation: To specify the target frequency for HDL Coder to modify the clock module setting in the reference design to produce the clock signal with that frequency. Enter a target frequency value that is in the Frequency Range (MHz). If you do not specify the target frequency, HDL Coder uses the Default (MHz) target frequency.
Simulink Real-Time FPGA I/O: For Speedgoat I/O modules that Xilinx ISE supports, specify the target frequency to generate the clock module to produce the clock signal with that frequency.
The Speedgoat^® I/O modules that are supported with Xilinx Vivado use the IP Core Generation workflow infrastructure. Specify the target frequency for HDL Coder to modify the clock module setting in the reference design to produce the clock signal with that frequency. Enter a target frequency value that is in the Frequency Range (MHz). If you do not specify the target frequency, HDL Coder uses the Default (MHz) target frequency.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify the TargetFrequency when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods.

Pass the parameter as an argument to the makehdl function.
```
makehdl('sfir_fixed/symmetric_fir', ... 
        'TargetFrequency',300)
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code by using makehdl.
```
hdlset_param('sfir_fixed','TargetFrequency',300)
makehdl('sfir_fixed/symmetric_fir')
```

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: TargetFrequency

Type: integer

Value: integer greater than or equal to 0

Default: 0

Limitations

When you use this parameter with the Treat Simulink rates as actual hardware rates parameter, the target frequency must be an integer multiple of the DUT base sample rate. HDL Coder computes the oversampling factor as the ratio of the target frequency to the base rate. If this ratio is not an integer, HDL Coder cannot determine a valid oversampling factor and cannot use the target frequency to set the generated clock rate.

For example, a target frequency of 50 MHz with a DUT base rate of 48 kHz produces a non-integer ratio, 50,000,000 / 48,000 = 1041.67. Choose a target frequency that is an integer multiple of the base rate, such as 48 MHz (48,000,000 / 48,000 = 1000).

Version History

Introduced in R2016a