Speed and Area Optimization
For your target hardware, generate HDL code from a MATLAB® function that meets timing and area requirements by using speed and area optimizations. Area optimizations reduce resource usage of your design. Speed optimizations improve the timing of your design on the target FPGA so that your design runs at higher frequencies by optimizing the critical path. To learn more about each type of optimization in HDL Coder™, see Speed and Area Optimizations in HDL Coder.
|Unroll or stream loops in generated HDL and SystemC code
|Insert pipeline registers at output of MATLAB expression
|Specify RAM mapping configuration for persistent array variables (Since R2023b)
|Apply neighborhood processing and element-wise operations to an incoming image or matrix for frame-to-sample conversion (Since R2022b)
|Apply iterative operation to an incoming image or matrix for frame-to-sample conversion (Since R2022b)
- Speed and Area Optimizations in HDL Coder
Learn about various speed and area optimizations and how to optimize your design.
- Specify the Clock Enable Rate
Configure clock enable to run at design base rate or input data rate.
- Minimize Clock Enables
Generate code for registers without clock enables.
- Constant Multiplier Optimization
What is Constant multiplier optimization and how to specify this optimization.
- Map Persistent Arrays and dsp.Delay Objects to RAM
Map persistent arrays and
dsp.Delayobjects to RAM on hardware to reduce the area used on your target device.
- Map Matrices to ROM
To map a matrix constant to ROM:If your MATLAB code meets these requirements, HDL Coder inserts a no-reset register at the output of the matrix in the generated code.
- Apply RAM Mapping to Optimize Area
Map elements to RAM to optimize area on your target hardware.
- Map Matrices to Block RAMs to Reduce Area
This example shows how to use the RAM mapping optimization in HDL Coder™ to map persistent matrix variables to block RAMs in hardware.
- Loop Streaming to Reduce Area
This example shows how to use the design-level loop streaming optimization in HDL Coder™ to optimize area.
- Pipelining MATLAB Code
Pipelining helps achieve a higher maximum clock rate by inserting registers at strategic points in the hardware to break the critical path.
- Pipeline MATLAB Expressions
Insert registers at output of MATLAB expression.
- Optimize MATLAB Loops
Optimize loops for area or speed.
- Distributed Pipelining
Distributed pipelining definition, benefits, and costs.
- Clock-Rate Pipelining
Pipeline registers insertion at the faster clock rate instead of the slower data rate.
- HDL Code Generation from Frame-Based Algorithms
Generate synthesizable HDL code from frame-based algorithms by using the HDL Coder frame-to-sample conversion to target sample-based and pixel-based hardware and reduce I/O consumption and prototyping times.
- Use Neighborhood, Reduction, and Iterator Patterns with a Frame-Based Model or Function for HDL Code Generation
Generate HDL code from a frame-based design that models neighborhood, reduction, and iterator patterns.