Resonant LLC Converter for Real-Time FPGA Deployment

Set Up Synthesis Tool Path

To synthesize the generated HDL code, before you use HDL Coder™ to generate code, set up your synthesis tool path. For example, if your synthesis tool is Xilinx® Vivado®, install the latest version of Xilinx Vivado as shown in HDL Language Support and Supported Third-Party Tools and Hardware.

Then, set the tool path to the installed Xilinx Vivado executable by using the hdlsetuptoolpath function. For example, this command sets the synthesis tool path to point to your installed Vivado® Design Suite 2024.1 batch file:

hdlsetuptoolpath("ToolName","Xilinx Vivado",...
"ToolPath","C:\Xilinx\Vivado\2024.1\bin\vivado.bat")

Resonant LLC Converter with Fixed-Point Data Type

This example shows the topology of a half-bridge resonant LLC converter with a full-bridge rectifier designed to run at a sample time of 20 ns. A resonant LLC converter is a DC-DC converter that uses a resonant tank circuit to achieve high efficiency and improved performance. It is widely used in applications requiring high efficiency and reliable operation, such as power supplies for servers, telecommunication equipment, and consumer electronics. The resonant LLC converter minimizes switching loss by achieving zero-voltage switching (ZVS). It can effectively regulate the output voltage across a wide range of load conditions. This is achieved through the unique design of the LLC resonant tank, which consists of two inductors (L) and one capacitor (C). The resonant frequency of this tank can be adjusted to ensure that the converter operates efficiently even at light loads.

In the resonant LLC converter represented in the model, the converter switches are triggered by a 100 kHz pulse with a duty cycle, D, of 0.5. In this topology, the switching bridge generates a square waveform to excite the LLC resonant tank. This, in turn, generates a resonant sinusoidal voltage that is stepped up or down by the transformer and then rectified by the rectifier circuit. The output capacitor filters the rectified voltage and outputs a DC voltage.

The data type precision for the model is set to fixed-point with a 36-bit word length. Using fixed-point precision determines the dynamic range of state-space matrices, and computes the appropriate fraction lengths and full-precision integer rounding modes by using the specified word length. This reduces resource utilization and improves FPGA sampling frequency.

The dynamic switch approximation method provides an improved FPGA sample rate, reduced resource utilization, and dead time stability, and prevents validation errors. To learn more about dynamic switch approximation, see Generate HDL Code for Simscape Models by Using Dynamic Switch Approximation.

Open the model at the MATLAB® command prompt.

open_system("sschdlexResonantLLCConverterExample")

The configurations inside the FPGA Subsystem block run on an FPGA board and the components that are outside the FPGA Subsystem block run on a CPU in real time. Open the FPGA Subsystem block that contains Simscape blocks.

open_system("sschdlexResonantLLCConverterExample/FPGA Subsystem")

The FPGA Subsystem block contains a pulse generator (PWM subsystem) and an LLC converter circuit (LLC Converter subsystem). You can generate VHDL®/Verilog® code for the blocks inside this FPGA Subsystem block.

Note: The resonant LLC converter model runs at a sample time of 20 ns. The CPU can achieve model time steps in microseconds. Downsample the sample time to 1 μs and pack 50 samples to one frame to log the output signals on the CPU at a rate of 50 μs. To learn more about CPU and FPGA data exchange, see Modeling Best Practices for FPGA HIL Deployment.

Run Desktop Simulation

The DC input voltage to the LLC Converter circuit is 340 V. The input signals (that include a PWM frequency and duty cycle) are provided to generate the gate pulses with a frequency of 100 kHz with 50% duty ratio in the FPGA Subsystem block of the model with the sample time of the Simscape model set to 20 ns.

To see the waveform, simulate the model.

sim("sschdlexResonantLLCConverterExample");

The scope provides the output voltage and inductor current waveform. Signal logging is enabled on the top level of the model. Double-click the Data Logger on top of the output signals to open the Simulation Data Inspector. Alternatively, to observe the waveform for the frame-based data representation, use these commands.

% Clear all plotted signals from subplot and set a 2-by-1 grid layout
Simulink.sdi.clearAllSubPlots
Simulink.sdi.setSubPlotLayout(2,1);

% Get the latest run identifiers
allIDs = Simulink.sdi.getAllRunIDs;
runID1 = allIDs(end);
run1 = Simulink.sdi.getRun(runID1);
run1.name = "Desktop Simulation";

% Get the two outputs (each generated after 50 delays)
Vout = run1.getSignalsByName("Output Voltage");
IL = run1.getSignalsByName("Inductor Current");

% Convert the output signals into frame-based data representation
Vout(1).convertToFrames;
IL(1).convertToFrames;

% Plot the resonant LLC converter output signals in the Simulation Data
% Inspector
plotOnSubPlot(Vout(1),1,1,true);
plotOnSubPlot(IL(1),2,1,true);

Simulink.sdi.view;

Generate HDL Code and Synthesize the Results

To generate the HDL code, first generate an HDL implementation model from the Simscape model by using the Simscape HDL Workflow Advisor. For details, see Generate Optimized HDL Implementation Model from Simscape.

After the task passes in the Advisor, you see a link to the generated HDL implementation model. You generate HDL code for this generated HDL implementation model and synthesize the HDL code. For details about the HDL code generation and synthesis of code, see Generate FPGA Bitstream for Two-Phase DC-DC Converter with Tunable Run-Time Parameters.

You can select the data type precision in the Generate implementation model task pane of the Simscape HDL Workflow Advisor.

The resonant LLC converter model is synthesized for Data type precision set to Fixed-point with Fixed-point word length set to 36-bit. The equivalent state-space model is generated with Validation logic tolerance set to 0.25 and the value of Target Frequency is set to 50.

Deploy Resonant LLC Converter to Speedgoat FPGA I/O Modules

In the HDL implementation model, the HDL Subsystem1 block contains blocks you run on the FPGA. You can run the HDL Workflow Advisor on this subsystem to deploy the HDL algorithm onto FPGA boards in Speedgoat target computers. For an example, see Deploy Simscape DC Motor Model to Speedgoat FPGA IO Module.