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Architecture Options for Cascaded Filters

You can specify unique serial, distributed arithmetic, or parallel architectures for each stage of cascade filters. These options lead to area efficient implementations of cascade filters, including Digital Down Converter (DDC), and Digital Up Converter (DUC) objects. You can use this feature only with the command-line interface (generatehdl). When you use the Generate HDL tool, each stage of a cascade uses the same architecture options.

You can pass a cell array of values to the SerialPartition, DALUTPartition, and DARadix properties, with each element corresponding to its respective stage. To skip the corresponding specification for a stage, specify the default value of that property. When you set a partition to a size of -1, the coder implements a parallel architecture for that stage.

PropertyDefault Value

When you create a cascaded filter, Filter Design HDL Coder™ software performs these actions:

  • Generates code for each stage as per the inferred architecture.

  • Generates an timing controller at the top level. This controller then produces clock enables for the module in each stage, which corresponds to the rate and folding factor of that module.


Use the hdlfilterserialinfo function to display the effective filter length and partitioning options for each filter stage of a cascade.

For examples, see