HDL code is generated in either VHDL or Verilog. The language you choose for code generation is called the target language. By default, the target language is VHDL. If you retain the VHDL setting, Generate HDL dialog box options that are specific to Verilog are disabled and are not selectable.
If you require or prefer to generate Verilog code, select
the Language option in the Target pane
of the Generate HDL dialog box. This setting causes the coder to enable
options that are specific to Verilog and to gray out and disable options
that are specific to VHDL.