setTriggerComparisonOperator

Configure operator that compares individual signal values within trigger condition

Syntax

setTriggerComparisonOperator(DC,name,operator)

setTriggerComparisonOperator(DC,name,operator,N)

Description

Add-On Required: This feature requires one of these add-ons.

• HDL Verifier Support Package for Intel FPGA Boards
• HDL Verifier Support Package for AMD FPGA and SoC Devices

setTriggerComparisonOperator(DC,name,operator) configures a comparison operator that compares individual signal values within the trigger condition in trigger stage 1. DC is a customized data capture object, name is the name of a trigger component signal.

setTriggerComparisonOperator(DC,name,operator,N) configures a comparison operator that compares individual signal values within the trigger condition in a trigger stage specified by N. DC is a customized data capture object, name is the name of a trigger component signal.

Input Arguments

DC — Customized data capture object

hdlverifier.FPGADataReader System object™

Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

name — Name of trigger component signal

character vector

Name of a trigger component signal, specified as a character vector. This name must match one of the signal names configured on creation of the input System object DC. The signal must be configured as a possible trigger signal.

operator — Operator to compare signals within trigger condition

== (default) | != | < | > | <= | >=

Operator to compare signals within the trigger condition, specified as one of these operators: == (default), !=, <, >, <=, or >=.

The trigger condition comprises value comparisons of one or more signals. For a multibit signal, specify one of these operators: == (default), !=, <, >, <=, or >=. For a trigger condition containing X or x (don't-care value), specify either == or != operators. For a logical signal, specify one of these operators: == or !=. For details on trigger conditions, see Triggers.

N — Trigger stage

integer from 1 to M

Trigger stage, specified as an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool. Use N to set the trigger comparison operator in Nth trigger stage. If you do not specify N, by default, the function sets the trigger comparison operator in trigger stage 1.

Version History

Introduced in R2019b