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Execute Free-Running FPGA-in-the-Loop

Generate Free-Running FIL Project

  1. Open the FPGA-in-the-Loop Wizard by entering the following command at the MATLAB® command prompt:

    filWizard
  2. Under FIL simulation with, select MATLAB System Object. Choose a supported board and a supported interface, for example, ZedBoard and Ethernet.

  3. Under MATLAB/FPGA Synchronization Mode, select Free-running FPGA. If necessary, adjust the DUT frequency in Advanced Options.

    FIL wizard open on the FIL Options screen, with the following settings: MATLAB System Object, ZedBoard, Ethernet, Free running

  4. Click Next.

  5. In the Source Files step, add the HDL source files and specify the top-level file of your DUT. For example:

    FIL wizard open on the Source Files screen, with DUT.v set as a file, and the top-level box selected.

  6. Click Next.

  7. In the DUT I/O Ports step, HDL Verifier™ parses the input and output ports of your DUT from the top file. It infers each port type from the HDL port name. Verify and modify the port type as needed.

    In this example, din1 and din2 are mapped as streaming data port type. din_valid is mapped to Streaming valid, and din_ready is mapped to Streaming ready. The ctrl and status ports are specified as Control data.

    FIL wizard open on the DUT I/O Ports screen, with ports mapped to inputs and outputs

  8. Complete the remaining steps to start the Vivado® project build. When the build is done, note the following artifacts in your working directory:

    • A project directory

    • A bit file

    • FIL class files

    Work directory highlighting the generated project directory, bit file, and FIL class files

Run FIL Simulation

Before you can run FIL with an FPGA board, you must configure the board and connect it to the host machine by using the Hardware Setup app.

To access help and a list of properties and methods for the free-running FIL class, enter the following command at the MATLAB command prompt:

help DUT_fil

Create FIL Object

Create a custom free-running FIL object from the class definition file generated by the FPGA-in-the-Loop Wizard.

obj = DUT_fil;

You can change writable properties as needed, for example:

obj.IPAddress = '192.168.1.101';

Program FPGA

To program the FPGA board, enter this command at the MATLAB prompt:

obj.programFPGA

Send Data

Use the writePort method to send data to DUT ports.

You can send a sample data to one control data port. For example:

obj.writePort("ctrl", <ctrlValue>);

where "ctrl" is the name of input control data port and <ctrlValue> is the port value.

You can send data to all streaming data ports. For example:

obj.writePort("din1", <din1Value>, "din2", <din2Value>);

where "din1" and "din2" are the names of input streaming data ports, and <din1Value> and <din2Value> are the port values, which must be the same length.

Receive Data

Use the readPort method to receive data from the DUT ports.

To receive a frame, you must first specify the frame length:

obj.ReadFrameLength = <frameLength>;

You can optionally specify a timeout for receiving data. Specify in units of seconds. The default value is 5 seconds.

obj.TimeOut = <timeOutInSec>;

You can receive data from all streaming data ports. For example:

[dout1Value, dout2Value] = obj.readPort("dout1","dout2");

where "dout1" and "dout2" are the names of output streaming ports, and dout1Value and dout2Value are the received frame data.

You can receive a sample data from one control data port at a time. For example:

statusValue = obj.readPort("status");

where "status" is the name of output control data port and statusValue is the port value.

Release Object

To release the connection with the FPGA board once you finish, enter this command at the MATLAB prompt:

obj.release;

See Also

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